Datasheet

Integrated I/O (IIO) Configuration Registers
350 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.5.29 QPI_CAP_ENABLE
Intel
®
QPI Capability Enable Register.
14.5.30 PCIE_CAP_ENABLE
PCI Express Capability Enable Register.
14.5.31 APICID_TAG_MAP
APICID to Tagged Map Register.
When DCA is disabled, DMA engine uses all 1s in the tag field of the write.
This register is setup by BIOS for the Intel® Quick Data driver to read. BIOS will map
APICID[7:5] to bits Tag[2:0]. BIOS should set Tag[4] to prevent implicit TPH cache
target unless it is intended.
Type: MEM PortID: 8’h7e
Bus: 0 Device: 4Function:0-7
Offset: 0x10c
Bit Attr Default Description
15:1 RV - Reserved.
0:0 RW 0x0
enable_prefetch_hint:
When set in function 0, DCA on Intel
®
QPI is enabled, else disabled. IIO
hardware does not use this bit from functions 1-7. In these functions, this bit
is provided primarily for BIOS to communicate to driver that DCA is enabled
in the IIO.
Type: MEM PortID: 8’h7e
Bus: 0 Device: 4Function:0-7
Offset: 0x10e
Bit Attr Default Description
15:1 RV - Reserved.
0:0 RW 0x0
enable_memwr_on_pcie:
When set in function 0, DCA on PCIe* is enabled, else disabled. IIO hardware
does not use this bit from functions 1-7. In these functions, this bit is
provided primarily for BIOS to communicate to driver that DCA is enabled in
the IIO.
Type: MEM PortID: 8’h7e
Bus: 0 Device: 4Function:0-7
Offset: 0x110
Bit Attr Default Description
63:40 RV - Reserved.