Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 359
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.6.7 CLSR
14.6.8 HDR
14.6.9 SVID
15:8 RO_V 0x80
sub_class:
Generic Device
7:0 RO_V 0x0
register_level_programming_interface:
Set to 00h for all non-APIC devices.
Type: CFG PortID: N/A
Bus: 0 Device: 5Function:0
Offset: 0xc
Bit Attr Default Description
7:0 RW 0x0
cacheline_size:
This register is set as RW for compatibility reasons only. Cacheline size is
always 64B.
Type: CFG PortID: N/A
Bus: 0 Device: 5Function:0
Offset: 0xe
Bit Attr Default Description
7:7 RO 0x1
multi_function_device:
This bit defaults to 1b since all these devices are multifunction
6:0 RO 0x0
configuration_layout:
This field identifies the format of the configuration header layout. It is Type 0
for all these devices. The default is 00h, indicating a “endpoint device”.
Type: CFG PortID: N/A
Bus: 0 Device: 5Function:0
Offset: 0x2c
Bit Attr Default Description
15:0 RW_O 0x8086
subsystem_vendor_identification_number:
The default value specifies Intel but can be set to any value once after reset.
Type: CFG PortID: N/A
Bus: 0 Device: 5Function:0
Offset: 0x9
Bit Attr Default Description