Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 373
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.6.39 CIPINTRC
Coherent Interface Protocol Interrupt Control.
28:26 RW 0x0
dcalt6:
For a TPH/DCA request, specifies the target NodeID[2:0] when the inverted
Tag[2:0] is 6
25:23 RW 0x0
dcalt5:
For a TPH/DCA request, specifies the target NodeID[2:0] when the inverted
Tag[2:0] is 5
22:20 RW 0x0
dcalt4:
For a TPH/DCA request, specifies the target NodeID[2:0] when the inverted
Tag[2:0] is 4
19:17 RW 0x0
dcalt3:
For a TPH/DCA request, specifies the target NodeID[2:0] when the inverted
Tag[2:0] is 3
16:14 RW 0x0
dcalt2:
For a TPH/DCA request, specifies the target NodeID[2:0] when the inverted
Tag[2:0] is 2
13:11 RW 0x0
dcalt1:
For a TPH/DCA request, specifies the target NodeID[2:0] when the inverted
Tag[2:0] is 1
10:8 RW 0x0
dcalt0:
For a TPH/DCA request, specifies the target NodeID[2:0] when the inverted
Tag[2:0] is 0
7:1 RV - Reserved.
0:0 RW 0x0
dcaen:
When disabled, PrefetchHint will not be sent on the coherent interface.
0: Disable TPH/DCA Prefetch Hints
1: Enable TPH/DCA Prefetch Hints
Notes:
This table is programmed by BIOS and this bit is set when the table is valid
Type: CFG PortID: N/A
Bus: 0 Device: 5Function:0
Offset: 0x148
Bit Attr Default Description
Type: CFG PortID: N/A
Bus: 0 Device: 5Function:0
Offset: 0x14c
Bit Attr Default Description
63:26 RV - Reserved.