Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 375
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.6.41 VTBAR
Base Address Register for Intel
®
VT-d.
14.6.42 VTGENCTRL
Intel
®
VT-d General Control.
30:30 RW1CS 0x0
nmi:
This is set whenever IIO forwards a VLW from PCH that had the NMI bit
asserted
29:7 RV - Reserved.
6:6 RO_V 0x0 nmi_ras_evt_pending:
5:5 RO_V 0x0 smi_ras_evt_pending:
4:4 RO_V 0x0 intr_evt_pending:
3:2 RV - Reserved.
1:1 RO_V 0x0 nmi_evt_pending:
0:0 RO_V 0x0
vlw_msgpend:
either generated internally or externally
Type: CFG PortID: N/A
Bus: 0 Device: 5Function:0
Offset: 0x154
Bit Attr Default Description
Type: CFG PortID: N/A
Bus: 0 Device: 5Function:0
Offset: 0x180
Bit Attr Default Description
31:13 RW_LB 0x0
vtd_chipset_base_address:
Provides an aligned 8K base address for IIO registers relating to
Intel
®
VT-d. All inbound accesses to this region are completer aborted by
the IIO.
12:1 RV - Reserved.
0:0 RW_LB 0x0
vtd_chipset_base_address_enable:
Note that accesses to registers pointed to by VTBAR are accessible via
message channel or JTAG mini-port, irrespective of the setting of this
enable bit that is, even if this bit is clear, read/write to Intel
®
VT-d registers
are completed normally (writes update registers and reads return the value
of the register) for accesses from message channel or JTAG mini-port.
This bit is RW_LB that is, lock is determined based on the “trusted” bit in
message channel when VTGENCTRL[15] is set, else it is RO.
Type: CFG PortID: N/A
Bus: 0 Device: 5Function:0
Offset: 0x184
Bit Attr Default Description
15:15 RW_O 0x0
lockvtd:
When this bit is 0, the VTBAR[0] is RW_LB, else it is RO.