Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 389
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.6.51 IRP_MISC_DFX0
2:2 RW_L 0x0
commandbit:
Writing a '1' to this bit will enable protection.
Writing a '0' to this bit will disable protection.
1:1 RO 0x0
protregsts:
IIO sets this bit when the protection has been enabled in hardware and for
all practical purposes this should be immediate. When protection is disabled,
then this bit is clear
0:0 RW_O 0x0
lock:
Bits 19:0 are locked down in this register when this bit is set. Can this be set
while other bits are being written to in the same write transaction
Type: CFG PortID: N/A
Bus: 0 Device: 5Function:0
Offset: 0x800
Bit Attr Default Description
31:31 RW_L 0x0
disable_pf_ack_bypass_path:
A bypass path for the pf_ack reduces latency by 3 cycles. This bit disables
the bypass.
30:30 RW_L 0x0
enable_parity_err_checking:
Enables Parity Error Checking in the IRP on the data received from the IIO
switch
29:29 RW_L 0x0
force_no_snp_on_vc1_vcm:
This force no snp on vc1 vcm transactions. this needs to be used in
conjunction with fast path disable for vc1 vcm transactions. otherwise switch
will receive an additional prh_done
28:28 RW_L 0x0
dump_pf_with_conflicts:
This is a performance optimization. if there is a wr pf that is followed by a
conflicting transaction, this just sends a fake pf_ack without sending it to
CBO.
27:27 RW_L 0x0
use_latest_rd_pf:
This is a performance optimization. if a rd pf 1, rd pf 2, rd f 1, rd f 2 is sent,
then the data from rd pf 2 is used for rd f 1. this is ok since the data being
sent is an even later version than what is ok.
26:26 RW_L 0x0
disregard_snum_while_merging:
Merges non back to back writes. might cause deadlock. needs to be used
with flush transactions on timeout knob
25:25 RW_L 0x0
disregard_posted_ordering:
Writes are sent in any random order. might cause deadlock. needs to be
used with aging timer rollover
Type: CFG PortID: N/A
Bus: 0 Device: 5Function:0
Offset: 0x290
Bit Attr Default Description