Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 403
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
23:20 RO 0xf
maximum_handle_mask_value:
IIO supports all 16 bits of handle being masked. Note IIO always
performs global interrupt entry invalidation on any interrupt cache
invalidation command and h/w never really looks at the mask
value.
19:18 RV - Reserved.
17:8 RO 0x20
invalidation_unit_offset:
IIO has the invalidation registers at offset 200h
7:7 RO 0x1
snoop_control:
0: Hardware does not support 1-setting of the SNP field in the
page-table entries.
1: Hardware supports the 1-setting of the SNP field in the page-
table entries.
IIO supports snoop override only for the nonisochronous
Intel
®
VT-d engine
6:6 RO 0x1
pass_through:
IIO supports pass through. This bit is RW_O for defeaturing in case
of post-si bugs.
5:5 RV - Reserved.
4:4 RW_O 0x1
ia32_extended_interrupt_mode:
IIO supports the extended interrupt mode
3:3 RO 0x1
interrupt_remapping_support:
IIO supports this
2:2 RW_O
0x1
(VTD0_EXT_CAP)
0x0
(VTD1_EXT_CAP)
device_tlb_support:
IIO supports ATS for the nonisochronous Intel
®
VT-d engine. This
bit is RW_O for nonisochronous engine in case we might have to
defeature ATS post-si.
1:1 RO 0x1
queued_invalidation_support:
IIO supports this
0:0 RW_O 0x0
coherency_support:
BIOS can write to this bit to indicate to hardware to either snoop or
not-snoop the DMA/Interrupt table structures in memory
(root/context/pd/pt/irt). Note that this bit is expected to be always
set to 0 for the Intel
®
VT-d engine and programmability is only
provided for that engine for debug reasons.
Type: MEM PortID: 8’h7e
Bus: 0 Device: 5Function:0
Offset: 0x10 , 0x1010
Bit Attr Default Description