Datasheet

Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family 415
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.7.23 NONISOCH_INVEVTDATA
Invalidation Event Data.
14.7.24 VTD[0:1]_INV_COMP_EVT_ADDR
Intel
®
VT-d Invalidation Completion Event Address.
14.7.25 VTD[0:1]_INV_COMP_EVT_UPRADDR
30:30 RO_V 0x0
inval_nonisoch_msi_pend:
Hardware sets the IP field whenever it detects an interrupt condition.
Interrupt condition is defined as:- An Invalidation Wait Descriptor with
Interrupt Flag (IF) field set completed, setting the IWC field in the Fault
Status register.
- If the IWC field in the Invalidation Event Status register was already set at
the time of setting this field, it is not treated as a new interrupt condition.
The IP field is kept set by hardware while the interrupt message is held
pending. The interrupt message could be held pending due to interrupt mask
(IM field) being set, or due to other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt message pending
condition is serviced. This could be due to either:
(a) Hardware issuing the interrupt message due to either change in the
transient hardware condition that caused interrupt message to be held
pending or due to software clearing the IM field.
(b) Software servicing the IWC field in the Fault Status register.
29:0 RO 0x0 inval_nonisoch_msgmsk_const:
Type: MEM PortID: 8’h7e
Bus: 0 Device: 5Function:0
Offset: 0xa0
Bit Attr Default Description
Type: MEM PortID: 8’h7e
Bus: 0 Device: 5Function:0
Offset: 0xa4
Bit Attr Default Description
31:16 RO 0x0 inval_nonisoch_data_const:
15:0 RW 0x0 inval_nonisoch_data:
Type: MEM PortID: 8’h7e
Bus: 0 Device: 5Function:0
Offset: 0xa8, 0x10a8
Bit Attr Default Description
31:2 RW 0x0 interrupt_address:
1:0 RV - reserved:
Type: MEM PortID: 8’h7e
Bus: 0 Device: 5Function:0
Offset: 0xac, 0x10ac
Bit Attr Default Description
31:0 RW 0x0 address: