Datasheet

Integrated I/O (IIO) Configuration Registers
416 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.7.26 VTD[0:1]_INTR_REMAP_TABLE_BASE
Intel
®
VT-d Interrupt Remapping Table Based Address.
14.7.27 VTD0_FLTREC[0:7]_GPA, VTD1_FLTREC0_GPA
Intel
®
VT-d Fault Record.
Type: MEM PortID: 8’h7e
Bus: 0 Device: 5Function:0
Offset: 0xb8, 0x10b8
Bit Attr Default Description
63:12 RW 0x0
intr_remap_base:
This field points to the base of page-aligned interrupt remapping table. If
the Interrupt Remapping Table is larger than 4 KB in size, it must be size-
aligned.Reads of this field returns value that was last programmed to it.
11:11 RW_LB 0x0
ia32_extended_interrupt_enable:
0: IA32 system is operating in legacy IA32 interrupt mode. Hardware
interprets only 8-bit APICID in the Interrupt Remapping Table entries.
1: IA32 system is operating in extended IA32 interrupt mode. Hardware
interprets 32-bit APICID in the Interrupt Remapping Table entries.
10:4 RV - Reserved.
3:0 RW 0x0
size:
This field specifies the size of the interrupt remapping table. The number of
entries in the interrupt remapping table is 2^(X+1), where X is the value
programmed in this field.
Type: MEM PortID: 8’h7e
Bus: 0 Device: 5Function:0
Offset: VTD0: 0x100, 0x110, 0x120, 0x130, 0x140, 0x150, 0x160, 0x170
VTD1: 0x1100
Bit Attr Default Description
63:12 ROS_V 0x0
gpa:
4K aligned GPA for the faulting transaction. valid only when F field is set.
11:0 RV - Reserved.