Datasheet

Integrated I/O (IIO) Configuration Registers
472 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.8.59 MIERRCTL
Miscellaneous Error Control.
14.8.60 MIFFERRST, MIFNERRST
Miscellaneous Fatal FERR and NERR Status.
14.8.61 MIFFERRHDR_[0:3]
Miscellaneous Fatal FERR Header Log. The header totally has 128 bits. Refer to the
below table for the mapping between Header and MIFFERRHDR_[0:3] registers.
Type: CFG PortID: N/A
Bus: 0 Device: 5 Function: 2
Offset: 0x384
Bit Attr Default Description
31:4 RV -
Reserved2:
Reserved.
3:3 RWS 0x0
vpp_err_sts:
VPP Error Status Enable.
2:0 RV -
Reserved1:
Reserved.
Type: CFG PortID: N/A
Bus: 0 Device: 5 Function: 2
Offset: 0x388, 0x39c
Bit Attr Default Description
31:11 RV - Reserved.
10:0 ROS_V 0x0 mi_err_st_log:
Bit Register Offset
127:96 MIFFERRHDR_3 0x398
95:64 MIFFERRHDR_2 0x394
63:32 MIFFERRHDR_1 0x390
31:0 MIFFERRHDR_0 0x38c
Type: CFG PortID: N/A
Bus: 0 Device: 5 Function: 2
Offset: 0x38c Size: 128 bits
Bit Attr Default Description
127:96 RV - Reserved.
95:95 ROS_V 0x0
vpp_reset_mode:
0: Power good reset will reset the VPP state machines and hard reset will
cause the VPP state machine to terminate at the next ’logical’ VPP stream
boundary and then reset the VPP state machines
1: Both power good and hard reset will reset the VPP state machines