Datasheet

Integrated I/O (IIO) Configuration Registers
498 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.11.4 PCISTS
0:0 RO 0x0
iose:
Not applicable to DFx and is hardwired to 0
Type: CFG PortID: N/A
Bus: 0 Device: 6Function:0,3
Bus: 0 Device: 7Function:0
Offset: 0x6
Bit Attr Default Description
15:15 RO 0x0
dpe:
Not applicable to DFx and is hardwired to 0
14:14 RO 0x0
sse:
Not applicable to DFx and is hardwired to 0
13:13 RO 0x0
rma:
Not applicable to DFx and is hardwired to 0
12:12 RO 0x0
rta:
Not applicable to DFx and is hardwired to 0
11:11 RO 0x0
sta:
Not applicable to DFx and is hardwired to 0
10:9 RO 0x0
devselt:
Not applicable to DFx and is hardwired to 0
8:8 RO 0x0
mdpe:
Not applicable to DFx and is hardwired to 0
7:7 RO 0x0
fb2b:
Not applicable to DFx and is hardwired to 0
6:6 RV - Reserved.
5:5 RO 0x0
pci66mhz_capable:
Not applicable to PCI Express. Hardwired to 0.
4:4 RO 0x1
capl:
This bit indicates the presence of a capabilities list structure.
3:3 RO 0x0
intxstat:
Not applicable to DFx and is hardwired to 0
2:0 RV - Reserved.
Type: CFG PortID: N/A
Bus: 0 Device: 6Function:0,3
Bus: 0 Device: 7Function:0
Offset: 0x4
Bit Attr Default Description