Datasheet

Registers Overview and Configuration Process
72 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
• Device 0: DMI2 Root Port. Logically this appears as a PCI device residing on PCI
Bus 0. Device 0 contains the standard PCI header registers, extended PCI
configuration registers and DMI2 device specific configuration registers.
• Device 2: PCI Express Root Port 2a, 2b, 2c and 2d. Logically this appears as a
“virtual” PCI-to-PCI bridge residing on PCI bus 0 and is compliant with PCI Express
Specification Revision 2.0. Device 2 contains the standard PCI Express/PCI
configuration registers including PCI Express Memory Address Mapping registers. It
also contains the extended PCI Express configuration space that include PCI
Express Link status/control registers and Virtual Channel controls.
• Device 3: PCI Express Root Port 3a, 3b, 3c and 3d. Logically this appears as a
“virtual” PCI-to-PCI bridge residing on PCI Bus 0 and is compliant with PCI Express
Local Bus Specification Revision 2.0. Device 3 contains the standard PCI
Express/PCI configuration registers including PCI Express Memory Address Mapping
registers. It also contains the extended PCI Express configuration space that
include PCI Express error status/control registers and Virtual Channel controls.
• Device 4: Intel
®
Quick Data DMA. This device contains the Standard PCI registers
for each of its functions. This device implements 8 functions for the 8 DMA
Channels and also contains Memory Map I/O registers.
• Device 5: Integrated I/O Core. This device contains the Standard PCI registers for
each of its functions. This device implements three functions; Function 0 contains
Address Mapping, Intel
®
Virtualization Technology (Intel
®
VT) for Directed I/O
(Intel
®
VT-d) related registers and other system management registers. Function 1
contains PCIe* and Memory Hot Plug registers. Function 2 contains I/O RAS
registers. Function 4 contains System Control/Status registers and miscellaneous
control/status registers on power management and throttling.
• Device 6, 7: PCI Express DFx. Contains the PCI Express Debug (DFx), Lock, Error
Injection Registers.
Figure 12-1. Processor integrated I/O device map
Bus= CPUBUSNO(0)
PCH
DMI2 Host
Bridge or PCIe*
Root Port
(Device 0)
Integrated I/O Core
(Device 5)
Memory Map/VTd
(Function 0)
Memory Hot Plug
(Function 1)
RAS (Function 2)
IOAPIC (Function 4)
PCIe Port 2 PCIe Port 3
PCIe Port 2a
(Dev#2, F#0)
PCIe Port 2b
(Dev#2, F#1)
PCIe Port 2c
(Dev#2, F#2)
PCIe Port 2d
(Dev#2, F#3)
PCIe Port 3a
(Dev#3, F#0)
PCIe Port 3b
(Dev#3, F#1)
PCIe Port 3c
(Dev#3, F#2)
PCIe Port 3d
(Dev#3, F#3)
Processor
DMA
Engine
(Device 4)
PCIe DFx
(Device 6, 7)