Datasheet

Processor Uncore Configuration Registers
96 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.1.6 RCOMP_TIMER
RCOMP wait timer.
Defines the time from IO starting to run RCOMP evaluation until RCOMP results are
definitely ready. This counter is added in order to keep determinism of the process if
operated in different mode.
This register also indicates that first RCOMP has been done.
5:5 RW_L 0x1
DDRIO Reset (internal logic) (reset_io):
Training Reset for DDRIO. It resets TX/RX FIFO pointers, and some read related
FSMs inside MCIO.
It goes to both the left and right DDRIO blocks on MC on only the left side
DDRIO block on Intel Xeon processor E7 v2 Series-based platform. Make sure
this bit is cleared before enabling DDRIO.
4:4 RW_L 0x1
IOSAV sequence channel sync (sync_iosav):
This bit is used in order to sync the IOSAV operation in four channels. It is
expect the BIOS to clear the bit after IOSAV test. Clearing the bit during test
may lead to unknown behavior. By setting it four channels get the enable
together.
3:3 RW_L 0x0
Refresh Enable (refresh_enable):
If cold reset, this bit should be set by BIOS after
1) Initializing the refresh timing parameters
2) Running DDR through reset ad init sequence.
If warm reset or S3 exit, this bit should be set immediately after SR exit.
2:2 RW_L 0x0 DCLK Enable (for all channels) (dclk_enable):
1:1 RW_L 0x1
DDR_RESET (ddr_reset):
DDR reset for all DIMM’s from all channels within this socket. No IMC/DDRIO
logic is reset by asserting this register.
It is important to note that this bit is negative logic. (that is, writing 0 to induce
a reset and write 1 for not reset.)
In Intel Xeon Processor E7 v2 product family, this field in both MC0 and MC1
need be programmed.
0:0 RV -
Reserved1:
Reserved.
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 0
Bus: 1 Device: 29 Function: 0
Offset: 0xb4
Bit Attr Default Description
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 0
Bus: 1 Device: 29 Function: 0
Offset: 0xc0
Bit Attr Default Description
31:31 RW_V 0x0
rcomp_in_progress:
rcomp in progress status bit.
30:22 RV - Reserved.