Datasheet

Processor Uncore Configuration Registers
98 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.1.9 MH_SENSE_500NS_CFG
MEMHOT Sense and 500ns Config.
17:17 RW 0x0
MHOT_EXT_SMI_EN (mhot_ext_smi_en):
Generate SMI event when either MEM_HOT[1:0]# is externally asserted.
16:16 RW 0x0
Enabling external MEM_HOT sensing logic (mh_sense_en):
Externally asserted MEM_HOT sense control enable bit.
When set, the MEM_HOT sense logic is enabled.
15:15 RW 0x1
Enabling mem_hot output generation logic (mh_output_en):
MEMHOT output generation logic enable control.
When 0, the MEM_HOT output generation logic is disabled, i.e.
MEM_HOT[1:0]# outputs are in deasserted state, no assertion regardless of
the memory temperature. Sensing of externally asserted MEM_HOT[1:0]#
is not affected by this bit. iMC will always reset the MH1_DIMM_VAL and
MH0_DIMM_VAL bits in the next DCLK so there is no impact to the PCU
microcode update to the MH_TEMP_STAT registers.
When 1, the MEM_HOT output generation logic is enabled.
14:0 RV -
Reserved1:
Reserved.
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 0
Bus: 1 Device: 29 Function: 0
Offset: 0x104
Bit Attr Default Description
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 0
Bus: 1 Device: 29 Function: 0
Offset: 0x10c
Bit Attr Default Description
31:26 RV - Reserved.
25:16 RW 0xc8
MH_SENSE_PERIOD (mh_sense_period):
MEMHOT Input Sense Period in number of CNTR_500_NANOSEC. BIOS
calculate number of CNTR_500_NANOSEC for 50 micro-sec / 100 micro-sec
/200 micro-sec / 400 micro-sec.
15:13 RW 0x2
MH_IN_SENSE_ASSERT (mh_in_sense_assert):
MEMHOT Input Sense Assertion Time in number of CNTR_500_NANOSEC. BIOS
calculate number of CNFG_500_NANOSEC for 1 micro-sec / 2 micro-sec
input_sense duration
Here is MH_IN_SENSE_ASSERT ranges:
0 or 1 Reserved
2 - 7 1 micro-sec - 3.5 micro-sec sense assertion time in 500nsec increment
12:10 RV - Reserved.