2nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop Datasheet, Volume 2 Supporting: Intel® Core™ i7, i5 and i3 Desktop Processor Series Intel® Pentium® G800 and G600 Desktop Processor Series Intel® Celeron® G500 and G400 Desktop Processor Series This is Volume 2 of 2 September 2011 Document Number: 324642-003
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Contents 1 Introduction ............................................................................................................ 11 2 Processor Configuration Registers ........................................................................... 13 2.1 Register Terminology ......................................................................................... 13 2.2 PCI Devices and Functions on Processor ............................................................... 14 2.3 System Address Map .......
2.6 4 2.5.8 SVID—Subsystem Vendor Identification Register......................................54 2.5.9 SID—Subsystem Identification Register ..................................................54 2.5.10 PXPEPBAR—PCI Express Egress Port Base Address Register .......................55 2.5.11 MCHBAR—Host Memory Mapped Register Range Base Register ..................56 2.5.12 GGC—GMCH Graphics Control Register Register .......................................57 2.5.13 DEVEN—Device Enable Register................
2.7 2.8 2.9 2.10 2.6.30 MC—Message Control Register ............................................................ 108 2.6.31 MA—Message Address Register ........................................................... 109 2.6.32 MD—Message Data Register ............................................................... 109 2.6.33 PEG_CAPL—PCI Express-G Capability List Register ................................. 109 2.6.34 PEG_CAP—PCI Express-G Capabilities Register ...................................... 110 2.6.
2.11 2.12 6 2.10.9 PBUSN6—Primary Bus Number Register................................................ 150 2.10.10 SBUSN6—Secondary Bus Number Register............................................ 151 2.10.11 SUBUSN6—Subordinate Bus Number Register ....................................... 151 2.10.12 IOBASE6—I/O Base Address Register ................................................... 152 2.10.13 IOLIMIT6—I/O Limit Address Register .................................................. 152 2.10.
2.13 2.14 2.15 2.16 2.17 2.18 2.12.14 DMIESD—DMI Element Self Description Register ................................... 196 2.12.15 DMILE1D—DMI Link Entry 1 Description Register................................... 197 2.12.16 DMILE1A—DMI Link Entry 1 Address Register........................................ 197 2.12.17 DMILE2D—DMI Link Entry 2 Description Register................................... 198 2.12.18 DMILE2A—DMI Link Entry 2 Address Register........................................ 198 2.12.
2.19 2.20 2.21 8 2.18.16 PLMLIMIT_REG—Protected Low-Memory Limit Register ........................... 241 2.18.17 PHMBASE_REG—Protected High-Memory Base Register .......................... 242 2.18.18 PHMLIMIT_REG—Protected High-Memory Limit Register .......................... 243 2.18.19 IQH_REG—Invalidation Queue Head Register......................................... 244 2.18.20 IQT_REG—Invalidation Queue Tail Register ........................................... 244 2.18.
2.21.27 2.21.28 2.21.29 IRTA_REG—Interrupt Remapping Table Address Register........................ 292 IVA_REG—Invalidate Address Register ................................................. 293 IOTLB_REG—IOTLB Invalidate Register ................................................ 294 Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 System Address Range Example ......................................................................... 17 DOS Legacy Address Range .......................................................
Revision History Revision Number Description Revision Date January 2011 001 • Initial release 002 • • • Added Intel® Pentium® processor family desktop Updated DSTS-Device Status Register (B/D/F/Type: 0/1/0/PCI) Added four registers to Section 2.13, MCHBAR Registers in Memory Controller – Channel 0. Added four registers to Section 2.
Introduction 1 Introduction This is Volume 2 of the Datasheet for the following products: • 2nd Generation Intel® Core™ processor family desktop • Intel® Pentium® processor family desktop • Intel® Celeron® processor family desktop The processor contains one or more PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket.
Introduction 12 Datasheet, Volume 2
Processor Configuration Registers 2 Processor Configuration Registers This chapter contains the following: • Register terminology • PCI Devices and Functions on processor • System address map • Processor register introduction • Detailed register bit descriptions 2.1 Register Terminology Table 2-1 shows the register-related terminology and register attributes that are used in this document. Attribute modifiers are listed in Table 2-2. Table 2-1.
Processor Configuration Registers Table 2-2. Register Attribute Modifiers Attribute Modifier Applicable Attribute Description RO (w/ -V) S RW RW1C Sticky: These bits are only re-initialized to their default value by a "Power Good Reset". Note: Does not apply to RO (constant) bits. RW1S -K -L RW RW WO RW -O -FW -V 2.
Processor Configuration Registers 2.3 System Address Map The processor supports 512 GB (39 bit) of addressable memory space and 64 KB+3 of addressable I/O space. This section focuses on how the memory space is partitioned and what the separate memory regions are used for. I/O address space has simpler mapping and is explained near the end of this section. The processor supports PEG port upper prefetchable base/limit registers. This allows the PEG unit to claim I/O accesses above 32 bit.
Processor Configuration Registers • Device 6, Function 0 — MBASE/MLIMIT – PCI Express port non-prefetchable memory access window. — PMBASE/PMLIMIT – PCI Express port prefetchable memory access window. — PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access window — IOBASE/IOLIMIT – PCI Express port I/O access window. • Device 2, Function 0 — IOBAR – I/O access window for internal graphics.
Processor Configuration Registers Figure 2-1. System Address Range Example PHYSICAL MEMORY (DRAM CONTROLLER VIEW) HOST/SYSTEM VIEW 512 GB PCI Memory Add. Range TOUUD BASE Reclaim Limit = Reclaim Base + x 1 MB aligned Reclaim BASE (subtractively decoded to DMI) TOM Main Memory Reclaim Add Range 1 MB aligned ME-UMA MESEG BASE 1 MB aligned 1 MB aligned Main memory Address Range Flash, APIC Intel TXT (20 MB) FEC0_0000 TOLUD BASE PCI Memory Add.
Processor Configuration Registers 2.3.1 Legacy Address Range This area is divided into the following address regions: • 0–640 KB – DOS Area • 640–768 KB – Legacy Video Buffer Area • 768–896 KB in 16 KB sections (total of 8 sections) – Expansion Area • 896–960 KB in 16 KB sections (total of 4 sections) – Extended System BIOS Area • 960 KB–1 MB Memory – System BIOS Area Figure 2-2.
Processor Configuration Registers 2.3.1.2 Legacy Video Area (A_0000h–B_FFFFh) The legacy 128 KB VGA memory range, frame buffer, (000A_0000h–000B_FFFFh) can be mapped to IGD (Device 2), to PCI Express (Device 1 or Device 6), and/or to the DMI Interface. The appropriate mapping depends on which devices are enabled and the programming of the VGA steering bits. Based on the VGA steering bits, priority for VGA mapping is constant. The processor always decodes internally mapped devices first.
Processor Configuration Registers 2.3.1.3 PAM (C_0000h–F_FFFFh) The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory Area. Each section has Read enable and Write enable attributes. The PAM registers are mapped in Device 0 configuration space. • ISA Expansion Area (C_0000h–D_FFFFh) • Extended System BIOS Area (E_0000h–E_FFFFh) • System BIOS Area (F_0000h–F_FFFFh) The processor decodes the Core request, then routes to the appropriate destination (DRAM or DMI).
Processor Configuration Registers 2.3.2.1 ISA Hole (15 MB–16 MB) The ISA Hole is enabled in the Legacy Access Control Register in Device 0 configuration space. If no hole is created, the processor will route the request to DRAM. If a hole is created, the processor will route the request to DMI, since the request does not target DRAM. Graphics translated requests to the range will always route to DRAM. 2.3.2.
Processor Configuration Registers for managing DMA accesses to addresses above 4 GB. DMA-remapping hardware implementations on platforms supporting Intel TXT are required to support protected high-memory region6, if the platform supports main memory above 4 GB. Once the protected low/high memory region registers are configured, bus master protection to these regions is enabled through the Protected Memory Enable register.
Processor Configuration Registers 2.3.2.6 Graphics Stolen Spaces 2.3.2.6.1 GTT Stolen Memory Space (GSM) GSM is allocated to store the graphics translation table entries. GSM always exists regardless of VT-d as long as internal graphics is enabled. This space is allocated to store accesses as page table entries are getting updated through virtual GTTMMADR range. Hardware is responsible to map PTEs into this physical space.
Processor Configuration Registers There are sub-ranges within the PCI Memory address range defined as APIC Configuration Space, MSI Interrupt Space, and High BIOS Address Range. The exceptions listed above for internal graphics and the PCI Express ports MUST NOT overlap with these ranges. Figure 2-4.
Processor Configuration Registers 2.3.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in the PCH portion of the chip-set, but may also exist as stand-alone components like PXH. The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be populated in the system.
Processor Configuration Registers 2.3.4 Main Memory Address Space (4 GB to TOUUD) The processor supports 39-bit addressing. The maximum main memory size supported is 32 GB total DRAM memory. A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger. As a result, TOM, and TOUUD registers and REMAPBASE/REMAPLIMIT registers become relevant. The remap configuration registers exist to remap lost main memory space.
Processor Configuration Registers 2.3.4.1 Memory Re-claim Background The following are examples of Memory Mapped IO devices that are typically located below 4 GB: • High BIOS • TSEG • GFX stolen • GTT stolen • XAPIC • Local APIC • MSI Interrupts • Mbase/Mlimit • Pmbase/PMlimit • Memory Mapped IO space that supports only 32B addressing The processor provides the capability to re-claim the physical memory overlapped by the Memory Mapped IO logical address space.
Processor Configuration Registers 2.3.4.3 Memory Remapping An incoming address (referred to as a logical address) is checked to see if it falls in the memory re-map window. The bottom of the re-map window is defined by the value in the REMAPBASE register. The top of the re-map window is defined by the value in the REMAPLIMIT register. An address that falls within this window is remapped to the physical memory starting at the address defined by the TOLUD register. The TOLUD register must be 1 MB aligned.
Processor Configuration Registers Case 1 – Less than 4 GB of Physical Memory (no remap) Figure 2-5.
Processor Configuration Registers Case 2 – Greater than 4 GB of Physical Memory Figure 2-6. Case 2 – Greater than 4 GB of Physical Memory PHYSICAL MEMORY (DRAM CONTROLLER VIEW) HOST/SYSTEM VIEW 512 GB High PCI Memory Add.
Processor Configuration Registers The Remap window is inclusive of the Base and Limit addresses. In the decoder A[19:0] of the Remap Base Address are assumed to be 0s. Similarly, A[19:0] of the Remap Limit Address are assumed to be Fhs. Thus, the bottom of the defined memory range will be aligned to a megabyte boundary and the top of the defined range will be one less than a MB boundary.
Processor Configuration Registers Implementation Notes • Remap applies to transactions from all interfaces. All upstream PEG/DMI transactions that are snooped get remapped. • Upstream PEG/DMI transactions that are not snooped (“Snoop not required” attribute set) get remapped. • Upstream reads and writes above TOUUD are treated as invalid cycles. • Remapped addresses remap starting at TOLUD. They do not remap starting at TSEG_BASE.
Processor Configuration Registers 2.3.6 PCI Express* Graphics Attach (PEG) The processor can be programmed to direct memory accesses to a PCI Express interface. When addresses are within either of two ranges specified using registers in each PEG(s) configuration space. • The first range is controlled using the Memory Base Register (MBASE) and Memory Limit Register (MLIMIT) registers.
Processor Configuration Registers 2.3.7 Graphics Memory Address Ranges The MCH can be programmed to direct memory accesses to IGD when addresses are within any of five ranges specified using registers in the processor Device 2 configuration space. 1. The Graphics Memory Aperture Base Register (GMADR) is used to access graphics memory allocated using the graphics translation table. 2.
Processor Configuration Registers 2.3.8 System Management Mode (SMM) Unlike FSB platforms, the Core handles all SMM mode transaction routing. Also, the platform no longer supports HSEG. The processor will never allow I/O devices access to CSEG/TSEG/HSEG ranges. DMI Interface and PCI Express masters are not allowed to access the SMM space. Table 2-3. SMM regions SMM Space Enabled 2.3.
Processor Configuration Registers display initiated LP non-snoop writes (for display writing a KVM captured frame) to Intel ME stolen memory are allowed. 2.3.11 I/O Address Space The system agent generates either DMI Interface or PCI Express* bus cycles for all processor I/O accesses that it does not claim. Configuration Address Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA) are used to generate PCI configuration space access.
Processor Configuration Registers The effective size of the range is programmed by the plug-and-play configuration software and it depends on the size of I/O space claimed by the PCI Express device. The processor also forwards accesses to the Legacy VGA I/O ranges according to the settings in the PEG configuration registers BCTRL (VGA Enable) and PCICMD (IOAE), unless a second adapter (monochrome) is present on the DMI Interface/PCI (or ISA).
Processor Configuration Registers I/O cycles and configuration cycles are not supported in the upstream direction. The result will be an unsupported request completion status. DMI Interface Accesses to the Processor that Cross Device Boundaries The processor does not support transactions that cross device boundaries. This should never occur because PCI Express transactions are not allowed to cross a 4 KB boundary.
Processor Configuration Registers — No “pacer” arbitration or TWRR arbitration will occur. Never remaps to different port. (PCH takes care of Egress port remapping). The PCH will meter TCm ME accesses and Azalia TC1 access bandwidth. — Internal Graphics GMADR writes and GMADR reads are not supported. • VCm accesses — See the DMI2 specification for TC mapping to VCm. VCm access only map to Intel ME stolen DRAM.
Processor Configuration Registers 2.3.13.2 PCI Express* Interface Decode Rules All “SNOOP semantic” PCI Express transactions are kept coherent with processor caches. All “Snoop not required semantic” cycles must reference the direct DRAM address range. PCI-Express non-snoop initiated cycles are not snooped.
Processor Configuration Registers Figure 2-8. PEG Upstream VC0 Memory Map Upstream Initiated VC0 Cycle Memory Map 2TB TOM = total physical DRAM 64GB REMAPLIMIT TOUUD REMAPBASE 4GB FEE0_0000 – FEEF_FFFF( MSI) GMADR TOLUD TSEG_BASE TOLUD-(Gfx Stolen)-(Gfx GTT stolen) -(TSEG) TSEG_BASE - DPR A0000-BFFFF (VGA) mem writes peer write (if matching PEG range else invalid) mem reads Invalid transaction mem writes Route based on SNR bit. mem reads Route based on SNR bit.
Processor Configuration Registers Accesses to the VGA memory range are directed to IGD depend on the configuration. The configuration is specified by: • Internal Graphics Controller in Device 2 is enabled (DEVEN.D2EN bit 4) • Internal Graphics VGA in Device 0, function 0 is enabled through register GGC bit 1. • IGD memory accesses (PCICMD2 04 – 05h, MAE bit 1) in Device 2 configuration space are enabled.
Processor Configuration Registers For regions mapped outside of the IGD (or if IGD is disabled), the legacy VGA memory range A0000h–BFFFFh is mapped either to the DMI Interface or PCI Express depending on the programming of the VGA Enable bit in the BCTRL configuration register in the PEG configuration space, and the MDAPxx bits in the Legacy Access Control (LAC) register in Device 0 configuration space. The same register controls mapping VGA I/O address ranges.
Processor Configuration Registers Enable bit is not set. If the VGA enable bit is set, then accesses to I/O address range x3BCh–x3BFh are forwarded to DMI Interface. If the VGA enable bit is not set, then accesses to I/O address range x3BCh–x3BFh are treated just like any other I/O accesses. That is, the cycles are forwarded to PCI Express if the address is within IOBASE and IOLIMIT and ISA enable bit is not set; otherwise, they are forwarded to DMI Interface.
Processor Configuration Registers 2.4 Processor Register Introduction The processor contains two sets of software accessible registers, accessed using the Host processor I/O address space – Control registers and internal configuration registers. • Control registers are I/O mapped into the processor I/O space, which control access to PCI and PCI Express configuration space (see Section 2.4.1).
Processor Configuration Registers 2.4.1 I/O Mapped Registers The processor contains two registers that reside in the processor I/O address space— the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window. 2.
Processor Configuration Registers Table 2-7.
Processor Configuration Registers 2.5.1 VID—Vendor Identification Register This register, combined with the Device Identification register, uniquely identifies any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.5.2 0/0/0/PCI 0–1h 8086h RO 16 bits Bit Attr Reset Value RST/ PWR 15:0 RO 8086h Uncore Description Vendor Identification Number (VID) PCI standard identification for Intel.
Processor Configuration Registers 2.5.3 PCICMD—PCI Command Register Since Device 0 does not physically reside on PCI_A, many of the bits are not implemented. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/PCI 4–5h 0006h RO, RW 16 bits 00h Bit Attr Reset Value 15:10 RO 0h Reserved 0b Uncore Fast Back-to-Back Enable (FB2B) This bit controls whether or not the master can do fast back-toback write.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.5.4 Attr 0/0/0/PCI 4–5h 0006h RO, RW 16 bits 00h Reset Value RST/ PWR Description 1 RO 1b Uncore Memory Access Enable (MAE) The processor always allows access to main memory, except when such access would violate security principles. Such exceptions are outside the scope of PCI control. This bit is not implemented and is hardwired to 1. Writes to this bit position have no effect.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 8 Datasheet, Volume 2 Attr RW1C 0/0/0/PCI 6–7h 0090h RO, RW1C 16 bits 00h Reset Value 0b 7 RO 1b 6 RO 0h 5 RO 0b 4 RO 1b 3:0 RO 0h RST/ PWR Description Uncore Master Data Parity Error Detected (DPD) This bit is set when DMI received a Poisoned completion from PCH. This bit can only be set when the Parity Error Enable bit in the PCI Command register is set.
Processor Configuration Registers 2.5.5 RID—Revision Identification Register This register contains the revision number of Device 0. These bits are read only and writes to this register have no effect. This register contains the revision number of the processor. The Revision ID (RID) is a traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function.
Processor Configuration Registers 2.5.6 CC—Class Code Register This register identifies the basic function of the device, a more specific sub-class, and a register-specific programming interface. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.5.7 0/0/0/PCI 9–Bh 06_0000h RO 24 bits Bit Attr Reset Value RST/ PWR Description 23:16 RO 06h Uncore Base Class Code (BCC) This is an 8-bit value that indicates the base class code for the Host Bridge device.
Processor Configuration Registers 2.5.8 SVID—Subsystem Vendor Identification Register This value is used to identify the vendor of the subsystem. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 15:0 2.5.9 Attr RW-O 0/0/0/PCI 2C–2Dh 0000h RW-O 16 bits Reset Value 0000h RST/ PWR Uncore Description Subsystem Vendor ID (SUBVID) This field should be programmed during boot-up to indicate the vendor of the system board. After it has been written once, it becomes read only.
Processor Configuration Registers 2.5.10 PXPEPBAR—PCI Express Egress Port Base Address Register This is the base address for the PCI Express Egress Port MMIO Configuration space. There is no physical memory within this 4 KB window that can be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the EGRESS port MMIO configuration space is disabled and must be enabled by writing a 1 to PXPEPBAREN [Device 0, offset 40h, bit 0].
Processor Configuration Registers 2.5.11 MCHBAR—Host Memory Mapped Register Range Base Register This is the base address for the Host Memory Mapped Configuration space. There is no physical memory within this 32 KB window that can be addressed. The 32 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the Host MMIO Memory Mapped Configuration space is disabled and must be enabled by writing a 1 to MCHBAREN [Device 0, offset 48h, bit 0].
Processor Configuration Registers 2.5.12 GGC—GMCH Graphics Control Register Register All the bits in this register are Intel TXT lockable. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/PCI 50–51h 0028h RW-KL, RW-L 16 bits 00h Bit Attr Reset Value 15 RO 0h 14 RW-L 0b 13:10 RO 0h Reserved 0h Uncore GTT Graphics Memory Size (GGMS) This field is used to select the amount of Main Memory that is preallocated to support the Internal Graphics Translation Table.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 58 0/0/0/PCI 50–51h 0028h RW-KL, RW-L 16 bits 00h Bit Attr Reset Value RST/ PWR 2 RO 0h Reserved Description 1 RW-L 0b Uncore IGD VGA Disable (IVD) 0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the Sub-Class Code within Device 2 Class Code register is 00. 1 = Disable.
Processor Configuration Registers 2.5.13 DEVEN—Device Enable Register This register allows for enabling/disabling of PCI devices and functions that are within the processor package. In the following table the bit definitions describe the behavior of all combinations of transactions to devices controlled by this register. All the bits in this register are Intel TXT Lockable.
Processor Configuration Registers 2.5.14 PCIEXBAR—PCI Express Register Range Base Address Register This is the base address for the PCI Express configuration space. This window of addresses contains the 4 KB of configuration space for each PCI Express device that can potentially be part of the PCI Express Hierarchy associated with the Uncore. There is no actual physical memory within this window of up to 256 MB that can be addressed. The actual size of this range is determined by a field in this register.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/PCI 60–67h 0000_0000_0000_0000h RW, RW-V 64 bits 0000_0000_0000h Bit Attr Reset Value 63:39 RO 0h RST/ PWR Description Reserved 38:28 RW 000h Uncore PCI Express Base Address (PCIEXBAR) This field corresponds to bits 38:28 of the base address for PCI Express enhanced configuration space.
Processor Configuration Registers 2.5.15 DMIBAR—Root Complex Register Range Base Address Register This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the Host Bridge. There is no physical memory within this 4 KB window that can be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space.
Processor Configuration Registers 2.5.16 PAM0—Programmable Attribute Map 0 Register This register controls the read, write and shadowing attributes of the BIOS range from F_0000h to F_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.17 PAM1—Programmable Attribute Map 1 Register This register controls the read, write and shadowing attributes of the BIOS range from C_0000h to C_7FFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.18 PAM2—Programmable Attribute Map 2 Register This register controls the read, write and shadowing attributes of the BIOS range from C_8000h to C_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.19 PAM3—Programmable Attribute Map 3 Register This register controls the read, write and shadowing attributes of the BIOS range from D0000h to D7FFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.20 PAM4—Programmable Attribute Map 4 Register This register controls the read, write and shadowing attributes of the BIOS range from D8000h to DFFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.21 PAM5—Programmable Attribute Map 5 Register This register controls the read, write and shadowing attributes of the BIOS range from E_0000h to E_7FFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.22 PAM6—Programmable Attribute Map 6 Register This register controls the read, write and shadowing attributes of the BIOS range from E_8000h to E_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.23 LAC—Legacy Access Control Register This 8-bit register controls steering of MDA cycles and a fixed DRAM hole from 1516 MB. There can only be at most one MDA device in the system. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Hole Enable (HEN) This field enables a memory hole in DRAM space. The DRAM that lies "behind" this space is not remapped. 0 = No memory hole. 1 = Memory hole from 15 MB to 16 MB.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2 Datasheet, Volume 2 Attr RW 0/0/0/PCI 87h 00h RW 8 bits 0h Reset Value 0b RST/ PWR Description Uncore PEG12 MDA Present (MDAP12) This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 2 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 1 72 Attr RW 0/0/0/PCI 87h 00h RW 8 bits 0h Reset Value 0b RST/ PWR Description Uncore PEG11 MDA Present (MDAP11) This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 1 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 0 Datasheet, Volume 2 Attr RW 0/0/0/PCI 87h 00h RW 8 bits 0h Reset Value 0b RST/ PWR Description Uncore PEG10 MDA Present (MDAP10) This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 0 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges.
Processor Configuration Registers 2.5.24 REMAPBASE—Remap Base Address Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.5.25 0/0/0/PCI 90–97h 0000_000F_FFF0_0000h RW-KL, RW-L 64 bits 0000_0000_0000h Bit Attr Reset Value 63:36 RO 0h 35:20 RW-L FFFFh 19:1 RO 0h 0 RW-KL 0b Description Reserved Uncore Remap Base Address (REMAPBASE) The value in this register defines the lower boundary of the Remap window. The Remap window is inclusive of this address.
Processor Configuration Registers 2.5.26 TOM—Top of Memory Register This register contains the size of physical memory. BIOS determines the memory size reported to the OS using this register.
Processor Configuration Registers 2.5.27 TOUUD—Top of Upper Usable DRAM Register This 64-bit register defines the Top of Upper Usable DRAM. Configuration software must set this value to TOM minus all Intel ME stolen memory if reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit + 1 byte, 1 MB aligned, since reclaim limit is 1 MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison.
Processor Configuration Registers 2.5.28 BDSM—Base Data of Stolen Memory Register This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0, offset BCh, bits 31:20). B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.5.
Processor Configuration Registers 2.5.30 G Memory Base Register This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory (PCI Device 0, Offset B4h, bits 31:20). Note: BIOS must program TSEGMB to a 8 MB naturally aligned boundary.
Processor Configuration Registers 2.5.31 TOLUD—Top of Low Usable DRAM Register This 32 bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics memory and Graphics Stolen Memory are within the DRAM space defined. From the top, the Host optionally claims 1 to 64 MBs of DRAM for internal graphics if enabled, 1 or 2 MB of DRAM for GTT Graphics Stolen Memory (if enabled) and 1, 2, or 8 MB of DRAM for TSEG if enabled. Programming Example: • C1DRB3 is set to 4 GB.
Processor Configuration Registers 2.5.32 SKPD—Scratchpad Data Register This register holds 32 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers. B/D/F/Type: Address Offset: Reset Value: Access: Size: 80 0/0/0/PCI DC–DFh 0000_0000h RW 32 bits Bit Attr Reset Value RST/ PWR 31:0 RW 0000_000 0h Uncore Description Scratchpad Data (SKPD) 1 DWORD of data storage.
Processor Configuration Registers 2.5.33 CAPID0_A—Capabilities A Register This register control of bits in this register are only required for customer visible SKU differentiation.
Processor Configuration Registers B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default: Bit Attr Reset Value 7:4 RO-FW 0h Reserved 3:3 RO 0h Reserved 2:0 82 0/0/0/PCI E4–E7h 0000_0000h RO-FW, RO-KFW 32 bits 000000h RO-FW 000b RST/ PWR Uncore Description DDR3 Maximum Frequency Capability (DMFC) This field controls which values may be written to the Memory Frequency Select field 6:4 of the Clocking Configuration registers (MCHBAR Offset C00h).
Processor Configuration Registers 2.6 PCI Device 1, Function 0–2 Configuration Registers Table 2-8 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-8. PCI Device 1, Function 0–2 Configuration Register Address Map (Sheet 1 of 2) Address Offset Register Symbol 0–1h VID1 Reset Value Access Vendor Identification 8086h RO Device Identification See Section 2.
Processor Configuration Registers Table 2-8.
Processor Configuration Registers 2.6.1 VID1—Vendor Identification Register This register combined with the Device Identification register uniquely identify any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.6.2 0/1/0–2/PCI 0–1h 8086h RO 16 bits Bit Attr Reset Value RST/ PWR 15:0 RO 8086h Uncore Description Vendor Identification (VID) PCI standard identification for Intel.
Processor Configuration Registers 2.6.3 PCICMD1—PCI Command Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 86 0/1/0–2/PCI 4–5h 0000h RW, RO 16 bits 00h Bit Attr Reset Value RST/ PWR 15:11 RO 0h Reserved Description 10 RW 0b Uncore INTA Assertion Disable (INTAAD) 0 = This device is permitted to generate INTA interrupt messages. 1 = This device is prevented from generating interrupt messages.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2 Datasheet, Volume 2 Attr RW 0/1/0–2/PCI 4–5h 0000h RW, RO 16 bits 00h Reset Value 0b RST/ PWR Description Uncore Bus Master Enable (BME) This bit controls the ability of the PEG port to forward Memory Read/Write Requests in the upstream direction. 0 = This device is prevented from making memory requests to its primary bus.
Processor Configuration Registers 2.6.4 PCISTS1—PCI Status Register This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express bridge embedded within the Root port.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Datasheet, Volume 2 Attr 0/1/0–2/PCI 6–7h 0010h RW1C, RO, RO-V 16 bits 0h Reset Value RST/ PWR Description 8 RW1C 0b Uncore Master Data Parity Error (PMDPE) This bit is Set by a Requester (Primary Side for Type 1 Configuration Space header Function) if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: • Requester receives a
Processor Configuration Registers 2.6.5 RID1—Revision Identification Register This register contains the revision number of the processor root port. These bits are read only and writes to this register have no effect. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 7:4 3:0 2.6.
Processor Configuration Registers 2.6.7 CL1—Cache Line Size Register B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.6.8 0/1/0–2/PCI Ch 00h RW 8 bits Bit Attr Reset Value RST/ PWR 7:0 RW 00h Uncore Description Cache Line Size (CLS) Implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no impact on any PCI Express device functionality. HDR1—Header Type Register This register identifies the header layout of the configuration space.
Processor Configuration Registers 2.6.10 SBUSN1—Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the "virtual" bridge (that is, to PCI Express-G). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express-G. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.6.
Processor Configuration Registers 2.6.12 IOBASE1—I/O Base Address Register This register controls the processor to PCI Express-G I/O access routing based on the following formula: IO_BASE address IO_LIMIT Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4 KB boundary. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.6.
Processor Configuration Registers 2.6.14 SSTS1—Secondary Status Register SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI bridge embedded within the processor.
Processor Configuration Registers 2.6.15 MBASE1—Memory Base Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE address MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are readonly and return zeroes when read. This register must be initialized by the configuration software.
Processor Configuration Registers 2.6.16 MLIMIT1—Memory Limit Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE address MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are readonly and return zeroes when read. This register must be initialized by the configuration software.
Processor Configuration Registers 2.6.17 PMBASE1—Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
Processor Configuration Registers 2.6.18 PMLIMIT1—Prefetchable Memory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
Processor Configuration Registers 2.6.19 PMBASEU1—Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation.
Processor Configuration Registers 2.6.20 PMLIMITU1—Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation.
Processor Configuration Registers 2.6.22 INTRLINE1—Interrupt Line Register This register contains interrupt line routing information. The device itself does not use this value, rather it is used by device drivers and operating systems to determine priority and vector information. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 7:0 2.6.
Processor Configuration Registers 2.6.24 BCTRL1—Bridge Control Register This register provides extensions to the PCICMD register that are specific to PCI-to-PCI bridges. BCTRL1 provides additional control for the secondary interface (that is, PCI Express-G) as well as some bits that affect the overall behavior of the "virtual" HostPCI Express bridge embedded within the processor (such as, VGA compatible address ranges mapping).
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 1 0 Datasheet, Volume 2 Attr RW RW 0/1/0–2/PCI 3E–3Fh 0000h RW, RO 16 bits 0h Reset Value 0b 0b RST/ PWR Description Uncore SERR Enable (SERREN) 0 = No forwarding of error messages from secondary side to primary side that could result in an SERR. 1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register.
Processor Configuration Registers 2.6.25 PM_CAPID1—Power Management Capabilities Register B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 104 Attr 0/1/0–2/PCI 80–83h C803_9001h RO, RO-V 32 bits Reset Value RST/ PWR Description 31:27 RO 19h Uncore PME Support (PMES) This field indicates the power states in which this device may indicate PME wake using PCI Express messaging. D0, D3hot & D3cold.
Processor Configuration Registers 2.6.26 PM_CS1—Power Management Control/Status Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/1/0–2/PCI 84–87h 0000_0008h RO, RW 32 bits 000000h Bit Attr Reset Value 31:16 RO 0h 15 RO 0b Uncore PME Status (PMESTS) This bit indicates that this device does not support PME# generation from D3cold.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 1:0 2.6.27 Attr RW 0/1/0–2/PCI 84–87h 0000_0008h RO, RW 32 bits 000000h Reset Value 00b RST/ PWR Description Uncore Power State (PS) This field indicates the current power state of this device and can be used to set the device into a new power state.
Processor Configuration Registers 2.6.28 SS—Subsystem ID and Subsystem Vendor ID Register System BIOS can be used as the mechanism for loading the SSID/SVID values. These values must be preserved through power management transitions and a hardware reset. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.6.
Processor Configuration Registers 2.6.30 MC—Message Control Register System software can modify bits in this register, but the device is prohibited from doing so. If the device writes the same message multiple times, only one of those messages is ensured to be serviced. If all of them must be serviced, the device must not generate the same message again until the driver services the earlier one.
Processor Configuration Registers 2.6.31 MA—Message Address Register B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.6.32 0/1/0–2/PCI 94–97h 0000_0000h RW, RO 32 bits Bit Attr Reset Value RST/ PWR 31:2 RW 0000_000 0h Uncore Message Address (MA) Used by system software to assign an MSI address to the device. The device handles an MSI by writing the padded contents of the MD register to this address.
Processor Configuration Registers 2.6.34 PEG_CAP—PCI Express-G Capabilities Register This register indicates PCI Express device capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.6.35 0/1/0–2/PCI A2–A3h 0142h RO, RW-O 16 bits 0h Bit Attr Reset Value 15:14 RO 0h 13:9 RO 00h RST/ PWR Description Reserved Uncore Interrupt Message Number (IMN) Not Applicable or Implemented. Hardwired to 0.
Processor Configuration Registers 2.6.36 DCTL—Device Control Register This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register.
Processor Configuration Registers 2.6.37 DSTS—Device Status Register Reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this device, not errors messages received across the link.
Processor Configuration Registers 2.6.38 LCTL—Link Control Register This register allows control of PCI Express link. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/1/0–2/PCI B0–B1h 0000h RW, RO, RW-V 16 bits 00h Bit Attr Reset Value 15:12 RO 0h Reserved 0b Uncore Link Autonomous Bandwidth Interrupt Enable (LABIE) When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 6 5 RW RW-V Reset Value 0b 0b RST/ PWR Description Uncore Common Clock Configuration (CCC) 0 = Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock. 1 = Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock.
Processor Configuration Registers 2.6.39 LSTS—Link Status Register This register indicates PCI Express link status.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 9:4 3:0 2.6.40 Attr RO-V RO-V 0/1/0–2/PCI B2–B3h 1001h RO-V, RW1C, RO 16 bits 0h Reset Value 00h 1h RST/ PWR Description Uncore Negotiated Link Width (NLW) This field indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed).
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 16:15 Datasheet, Volume 2 Attr RW-O 0/1/0–2/PCI B4–B7h 0004_0000h RW-O, RO 32 bits Reset Value 00b RST/ PWR Description Uncore Slot Power Limit Scale (SPLS) This field specifies the scale used for the Slot Power Limit Value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x If this field is written, the link sends a Set_Slot_Power_Limit message.
Processor Configuration Registers 2.6.41 SLOTCTL—Slot Control Register PCI Express Slot related registers allow for the support of Hot Plug.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 7:6 5 RO RO Reset Value 00b 0b RST/ PWR Description Uncore Reserved for Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.
Processor Configuration Registers 2.6.42 SLOTSTS—Slot Status Register This is for PCI Express Slot related registers. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value 15:9 RO 0h Reserved 0b Uncore Reserved for Data Link Layer State Changed (DLLSC) This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Datasheet, Volume 2 Attr 0/1/0–2/PCI BA–BBh 0000h RO, RO-V, RW1C 16 bits 00h Reset Value RST/ PWR Description 3 RW1C 0b Uncore Presence Detect Changed (PDC) A pulse indication that the inband presence detect state has changed This bit is set when the value reported in Presence Detect State is changed.
Processor Configuration Registers 2.6.43 RCTL—Root Control Register This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link. Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register.
Processor Configuration Registers 2.6.44 LCTL2—Link Control 2 Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/1/0–2/PCI D0–D1h 0002h RWS, RWS-V 16 bits 0h Bit Attr Reset Value 15:13 RO 0h Reserved 0b Powerg ood Compliance De-emphasis (ComplianceDeemphasis) This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. 1 = -3.5 dB 0 = -6 dB When the Link is operating at 2.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description Powerg ood Selectable De-emphasis (selectabledeemphasis) When the Link is operating at 5GT/s speed, selects the level of deemphasis. Encodings: 1 = -3.5 dB 0 = -6 dB Reset Value is implementation specific, unless a specific value is required for a selected form factor or platform. When the Link is operating at 2.
Processor Configuration Registers 2.7 PCI Device 1, Function 0–2 Extended Configuration Registers Table 2-9 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-9. PCI Device 1, Function 0–2 Extended Configuration Register Address Map Address Offset 2.7.
Processor Configuration Registers 2.7.2 PVCCAP2—Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.7.3 Attr 0/1/0–2/MMR 108–10Bh 0000_0000h RO 32 bits 0000h Reset Value 31:24 RO 00h 23:8 RO 0h 7:0 RO 00h Description Uncore VC Arbitration Table Offset (VCATO) Indicates the location of the VC Arbitration Table.
Processor Configuration Registers 2.7.
Processor Configuration Registers 2.7.5 VC0RCTL—VC0 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 128 0/1/0–2/MMR 114–117h 8000_00FFh RO, RW 32 bits 000h Bit Attr Reset Value RST/ PWR Description 31 RO 1b Uncore VC0 Enable (VC0E) For VC0, this is hardwired to 1 and read only as VC0 can never be disabled.
Processor Configuration Registers 2.7.6 VC0RSTS—VC0 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.7.7 0/1/0–2/MMR 11A–11Bh 0002h RO-V 16 bits 0000h Bit Attr Reset Value 15:2 RO 0h Reserved VC0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Configuration Registers 2.8 PCI Device 2 Configuration Registers Table 2-10 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-10.
Processor Configuration Registers 2.8.1 VID2—Vendor Identification Register This register, combined with the Device Identification register, uniquely identifies any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.8.2 0/2/0/PCI 0-1h 8086h RO 16 bits Bit Attr Reset Value RST/ PWR 15:0 RO 8086h Uncore Description Vendor Identification Number (VID) PCI standard identification for Intel.
Processor Configuration Registers 2.8.3 PCICMD2—PCI Command Register This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value 15:11 RO 0h Reserved RST/ PWR Description 10 RW 0b FLR, Uncore Interrupt Disable (INTDIS) This bit disables the device from asserting INTx#.
Processor Configuration Registers 2.8.4 PCISTS2—PCI Status Register PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD.
Processor Configuration Registers 2.8.5 RID2—Revision Identification Register This register contains the revision number for Device 2 Functions 0. These bits are read only and writes to this register have no effect. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 7:4 3:0 2.8.6 Attr RO-FW RO-FW 0/2/0/PCI 8h 00h RO–FW 8 bits Reset Value 0h 0h RST/ PWR Description Uncore Revision Identification Number MSB (RID_MSB) Four MSB of RID.
Processor Configuration Registers 2.8.7 CLS—Cache Line Size Register The IGD does not support this register as a PCI slave. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 7:0 2.8.8 Attr RO 0/2/0/PCI Ch 00h RO 8 bits Reset Value 00h RST/ PWR Uncore Description Cache Line Size (CLS) This field is hardwired to 0s. The IGD as a PCI compliant master does not use the Memory Write and Invalidate command and, in general, does not perform operations based on cache line size.
Processor Configuration Registers 2.8.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address Register This register requests allocation for the combined Graphics Translation Table Modification Range and Memory Mapped Range. The range requires 4 MB combined for MMIO and Global GTT aperture, with 2MB of that used by MMIO and 2 MB used by GTT. GTTADR will begin at (GTTMMADR + 2 MB) while the MMIO base address will be the same as GTTMMADR.
Processor Configuration Registers 2.8.11 GMADR—Graphics Memory Range Address Register GMADR is the PCI aperture used by software to access tiled graphics surfaces in a linear fashion. B/D/F/Type: Address Offset: Reset Value: Access: Size: 0/2/0/PCI 18–1Fh 0000_0000_0000_000Ch RO, RW-L, RW 64 bits Bit Attr Reset Value RST/ PWR Description 63:39 RW 0000000h FLR, Uncore Reserved for Memory Base Address (RSVDRW) Must be set to 0 since addressing above 512 GB is not supported.
Processor Configuration Registers 2.8.12 IOBAR—I/O Base Address Register This register provides the Base offset of the I/O registers within Device 2. Bits 15:6 are programmable allowing the I/O Base to be located anywhere in 16-bit I/O Address Space. Bits 2:1 are fixed and return zero; bit 0 is hardwired to a one indicating that 8 bytes of I/O space are decoded. Access to the 8Bs of I/O space is allowed in PM state D0 when I/O Enable (PCICMD bit 0) is set.
Processor Configuration Registers 2.8.14 SID2—Subsystem Identification Register This register is used to uniquely identify the subsystem where the PCI device resides. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 15:0 2.8.15 Attr RW-O 0/2/0/PCI 2E–2Fh 0000h RW-O 16 bits Reset Value 0000h RST/ PWR Description Uncore Subsystem Identification (SUBID) This value is used to identify a particular subsystem. This field should be programmed by BIOS during boot-up.
Processor Configuration Registers 2.8.17 MINGNT—Minimum Grant Register The Integrated Graphics Device has no requirement for the settings of Latency Timers. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.8.18 0/2/0/PCI 3Eh 00h RO 8 bits Bit Attr Reset Value RST/ PWR 7:0 RO 00h Uncore Description Minimum Grant Value (MGV) The IGD does not burst as a PCI compliant master.
Processor Configuration Registers 2.8.19 MSAC—Multi Size Aperture Control Register This register determines the size of the graphics memory aperture in function 0 and in the trusted space. Only the system BIOS will write this register based on pre-boot address allocation efforts; however, the graphics may read this register to determine the correct aperture size. System BIOS needs to save this value on boot so that it can reset it correctly during S3 resume.
Processor Configuration Registers 2.9 Device 2 I/O Registers Table 2-11. Device 2 I/O Register Address Map 2.9.1 Address Offset Register Symbol 0–3h Index MMIO Address Register 0000_0000h RW 4–7h Data MMIO Data Register 0000_0000h RW Register Name Reset Value Access INDEX—MMIO Address Register A 32-bit I/O write to this port loads the offset of the MMIO register or offset into the GTT that needs to be accessed. An I/O Read returns the current value of this register.
Processor Configuration Registers 2.10 PCI Device 6 Configuration Registers Table 2-12 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-12.
Processor Configuration Registers Table 2-12.
Processor Configuration Registers 2.10.2 DID6—Device Identification Register This register, combined with the Vendor Identification register, uniquely identifies any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.10.3 0/6/0/PCI 2–3h 010Dh RO-FW 16 bits Bit Attr Reset Value RST/ PWR 15:0 RO-FW 010Dh Uncore Description Device Identification Number MSB (DID_MSB) Identifier assigned to the processor root port (virtual PCI-to-PCI bridge, PCI Express Graphics port).
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description 6 RW 0b Uncore Parity Error Response Enable (PERRE) Controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set. 0 = Master Data Parity Error bit in PCI Status register can NOT be set. 1 = Master Data Parity Error bit in PCI Status register CAN be set.
Processor Configuration Registers 2.10.4 PCISTS6—PCI Status Register This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express bridge embedded within the Root port.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 148 Attr 0/6/0/PCI 6–7h 0010h RW1C, RO, RO-V 16 bits 0h Reset Value RST/ PWR Description 8 RW1C 0b Uncore Master Data Parity Error (PMDPE) This bit is set by a Requester (Primary Side for Type 1 Configuration Space header Function) if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: • Requester receives a Completion marked
Processor Configuration Registers 2.10.5 RID6—Revision Identification Register This register contains the revision number of the processor root port. These bits are read only and writes to this register have no effect. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 7:4 3:0 2.10.
Processor Configuration Registers 2.10.7 CL6—Cache Line Size Register B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.10.8 0/6/0/PCI Ch 00h RW 8 bits Bit Attr Reset Value RST/ PWR 7:0 RW 00h Uncore Description Cache Line Size (CLS) Implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no impact on any PCI Express device functionality. HDR6—Header Type Register This register identifies the header layout of the configuration space.
Processor Configuration Registers 2.10.10 SBUSN6—Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the "virtual" bridge (that is, to PCI Express-G). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express-G. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.10.
Processor Configuration Registers 2.10.12 IOBASE6—I/O Base Address Register This register controls the processor to PCI Express-G I/O access routing based on the following formula: IO_BASE address IO_LIMIT Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4 KB boundary. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.10.
Processor Configuration Registers 2.10.14 SSTS6—Secondary Status Register SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI bridge embedded within the processor.
Processor Configuration Registers 2.10.15 MBASE6—Memory Base Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE address MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are readonly and return zeroes when read. This register must be initialized by the configuration software.
Processor Configuration Registers 2.10.16 MLIMIT6—Memory Limit Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE address MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are readonly and return zeroes when read. This register must be initialized by the configuration software.
Processor Configuration Registers 2.10.17 PMBASE6—Prefetchable Memory Base Address Register This register, in conjunction with the corresponding Upper Base Address register, controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
Processor Configuration Registers 2.10.18 PMLIMIT6—Prefetchable Memory Limit Address Register This register, in conjunction with the corresponding Upper Limit Address register, controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
Processor Configuration Registers 2.10.19 PMBASEU6—Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation.
Processor Configuration Registers 2.10.20 PMLIMITU6—Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation.
Processor Configuration Registers 2.10.22 INTRLINE6—Interrupt Line Register This register contains interrupt line routing information. The device itself does not use this value, rather it is used by device drivers and operating systems to determine priority and vector information. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 7:0 2.10.
Processor Configuration Registers 2.10.24 BCTRL6—Bridge Control Register This register provides extensions to the PCICMD register that are specific to PCI-to-PCI bridges. The BCTRL provides additional control for the secondary interface (that is, PCI Express-G) as well as some bits that affect the overall behavior of the "virtual" HostPCI Express bridge embedded within the processor (such as, VGA compatible address ranges mapping).
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 1 0 162 Attr RW RW 0/6/0/PCI 3E–3Fh 0000h RO, RW 16 bits 0h Reset Value 0b 0b RST/ PWR Description Uncore SERR Enable (SERREN) 0 = No forwarding of error messages from secondary side to primary side that could result in an SERR. 1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register.
Processor Configuration Registers 2.10.25 PM_CAPID6—Power Management Capabilities Register B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit Attr 0/6/0/PCI 80–83h C803_9001h RO, RO-V 32 bits Reset Value RST/ PWR Description 31:27 RO 19h Uncore PME Support (PMES) This field indicates the power states in which this device may indicate PME wake using PCI Express messaging. D0, D3hot, and D3cold.
Processor Configuration Registers 2.10.26 PM_CS6—Power Management Control/Status Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 164 0/6/0/PCI 84–87h 0000_0008h RO, RW 32 bits 000000h Bit Attr Reset Value RST/ PWR 31:16 RO 0h 15 RO 0b Uncore PME Status (PMESTS) This bit indicates that this device does not support PME# generation from D3cold.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 1:0 2.10.27 Attr RW 0/6/0/PCI 84–87h 0000_0008h RO, RW 32 bits 000000h Reset Value 00b RST/ PWR Description Uncore Power State (PS) This field indicates the current power state of this device and can be used to set the device into a new power state.
Processor Configuration Registers 2.10.28 SS—Subsystem ID and Subsystem Vendor ID Register System BIOS can be used as the mechanism for loading the SSID/SVID values. These values must be preserved through power management transitions and a hardware reset. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.10.
Processor Configuration Registers 2.10.30 MC—Message Control Register System software can modify bits in this register, but the device is prohibited from doing so. If the device writes the same message multiple times, only one of those messages is assured to be serviced. If all of them must be serviced, the device must not generate the same message again until the driver services the earlier one.
Processor Configuration Registers 2.10.31 MA—Message Address Register B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.10.32 0/6/0/PCI 94–97h 0000_0000h RW, RO 32 bits Bit Attr Reset Value RST/ PWR 31:2 RW 0000_000 0h Uncore Message Address (MA) This field is used by system software to assign an MSI address to the device. The device handles an MSI by writing the padded contents of the MD register to this address.
Processor Configuration Registers 2.10.34 PEG_CAP—PCI Express-G Capabilities Register This register indicates PCI Express device capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.10.35 0/6/0/PCI A2–A3h 0142h RO, RW-O 16 bits 0h Bit Attr Reset Value 15:14 RO 0h 13:9 RO 00h RST/ PWR Description Reserved Uncore Interrupt Message Number (IMN) Not Applicable or Implemented. Hardwired to 0.
Processor Configuration Registers 2.10.36 DCTL—Device Control Register This register provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register.
Processor Configuration Registers 2.10.37 DSTS—Device Status Register This register reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this device, not errors messages received across the link.
Processor Configuration Registers 2.10.38 LCTL—Link Control Register This register allows control of PCI Express link. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value 15:12 RO 0h Reserved 0b Uncore Link Autonomous Bandwidth Interrupt Enable (LABIE) When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 6 5 RW RW-V Reset Value 0b 0b RST/ PWR Description Uncore Common Clock Configuration (CCC) 0 = Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock. 1 = Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock.
Processor Configuration Registers 2.10.39 LSTS—Link Status Register This register indicates PCI Express link status.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 9:4 3:0 2.10.40 Attr RO-V RO-V 0/6/0/PCI B2–B3h 1001h RW1C, RO-V, RO 16 bits 0h Reset Value 00h 1h RST/ PWR Description Uncore Negotiated Link Width (NLW) This field indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed).
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 16:15 176 Attr RW-O 0/6/0/PCI B4–B7h 0004_0000h RW-O, RO 32 bits Reset Value 00b RST/ PWR Description Uncore Slot Power Limit Scale (SPLS) This field specifies the scale used for the Slot Power Limit Value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x If this field is written, the link sends a Set_Slot_Power_Limit message.
Processor Configuration Registers 2.10.41 SLOTCTL—Slot Control Register PCI Express Slot related registers allow for the support of Hot Plug.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 7:6 5 RO RO Reset Value 00b 0b RST/ PWR Description Uncore Reserved for Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.
Processor Configuration Registers 2.10.42 SLOTSTS—Slot Status Register This is for PCI Express Slot related registers. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value 15:9 RO 0h Reserved 0b Uncore Reserved for Data Link Layer State Changed (DLLSC) This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.10.43 Attr 0/6/0/PCI BA–BBh 0000h RO, RO-V, RW1C 16 bits 00h Reset Value RST/ PWR Description 3 RW1C 0b Uncore Presence Detect Changed (PDC) A pulse indication that the inband presence detect state has changed. This bit is set when the value reported in Presence Detect State is changed.
Processor Configuration Registers 2.11 PCI Device 6 Extended Configuration Registers Table 2-13 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-13. PCI Device 6 Extended Configuration Register Address Map 2.11.
Processor Configuration Registers 2.11.2 PVCCAP2—Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.11.3 Attr 0/6/0/MMR 108–10Bh 0000_0000h RO 32 bits 0000h Reset Value 31:24 RO 00h 23:8 RO 0h 7:0 RO 00h Description Uncore VC Arbitration Table Offset (VCATO) This field indicates the location of the VC Arbitration Table.
Processor Configuration Registers 2.11.
Processor Configuration Registers 2.11.5 VC0RCTL—VC0 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 184 0/6/0/MMR 114–117h 8000_00FFh RO, RW 32 bits 000h Bit Attr Reset Value RST/ PWR Description 31 RO 1b Uncore VC0 Enable (VC0E) For VC0, this is hardwired to 1 and read only as VC0 can never be disabled.
Processor Configuration Registers 2.11.6 VC0RSTS—VC0 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Datasheet, Volume 2 0/6/0/MMR 11A–11Bh 0002h RO-V 16 bits 0000h Bit Attr Reset Value 15:2 RO 0h Reserved VC0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Configuration Registers 2.12 DMIBAR Registers Table 2-14 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-14.
Processor Configuration Registers Table 2-14. DMIBAR Register Address Map (Sheet 2 of 2) Address Offset 2.12.
Processor Configuration Registers 2.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Channels associated with this port. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.
Processor Configuration Registers 2.12.4 DMIPVCCTL—DMI Port VC Control Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.5 0/0/0/DMIBAR C–Dh 0000h RW, RO 16 bits 000h Bit Attr Reset Value 15:4 RO 0h RST/ PWR Description Reserved 3:1 RW 000b Uncore VC Arbitration Select (VCAS) This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field.
Processor Configuration Registers 2.12.6 DMIVC0RCTL—DMI VC0 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 190 0/0/0/DMIBAR 14–17h 8000_007Fh RO, RW 32 bits 00000h Bit Attr Reset Value RST/ PWR Description 31 RO 1b Uncore Virtual Channel 0 Enable (VC0E) For VC0, this is hardwired to 1 and read only as VC0 can never be disabled.
Processor Configuration Registers 2.12.7 DMIVC0RSTS—DMI VC0 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.8 0/0/0/DMIBAR 1A–1Bh 0002h RO-V 16 bits 0000h Bit Attr Reset Value 15:2 RO 0h Reserved Virtual Channel 0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Configuration Registers 2.12.9 DMIVC1RCTL—DMI VC1 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 1. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 192 Attr 0/0/0/DMIBAR 20–23h 0100_0000h RO, RW 32 bits 00000h Reset Value 31 RW 0b 30:27 RO 0h 26:24 RW 001b 23:20 RO 0h 19:17 RW 000b 16:8 RO 0h 7 RO 0b RST/ PWR Description Uncore Virtual Channel 1 Enable (VC1E) 0 = Disabled.
Processor Configuration Registers 2.12.10 DMIVC1RSTS—DMI VC1 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.11 0/0/0/DMIBAR 26–27h 0002h RO-V 16 bits 0000h Bit Attr Reset Value 15:2 RO 0h Reserved Virtual Channel 1 Negotiation Pending (VC1NP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Configuration Registers 2.12.12 DMIVCPRCTL—DMI VCp Resource Control Register This register controls the resources associated with the DMI Private Channel (VCp). B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 194 Attr 0/0/0/DMIBAR 2C–2Fh 0200_0000h RO, RW 32 bits 00000h Reset Value 31 RW 0b 30:27 RO 0h 26:24 RW 010b 23:8 RO 0h 7 RO 0b RST/ PWR Description Uncore Virtual Channel private Enable (VCPE) 0 = Virtual Channel is disabled.
Processor Configuration Registers 2.12.13 DMIVCPRSTS—DMI VCp Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Datasheet, Volume 2 0/0/0/DMIBAR 32–33h 0002h RO-V 16 bits 0000h Bit Attr Reset Value 15:2 RO 0h Reserved Virtual Channel private Negotiation Pending (VCPNP) 0 = The VC negotiation is complete.
Processor Configuration Registers 2.12.14 DMIESD—DMI Element Self Description Register This register provides information about the root complex element containing this Link Declaration Capability.
Processor Configuration Registers 2.12.15 DMILE1D—DMI Link Entry 1 Description Register This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 31:24 2.12.
Processor Configuration Registers 2.12.17 DMILE2D—DMI Link Entry 2 Description Register This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 31:24 2.12.
Processor Configuration Registers 2.12.19 LCAP—Link Capabilities Register This register indicates DMI specific capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/DMIBAR 84–87h 0001_2C41h RW-O, RO, RW-OV 32 bits 00002h Bit Attr Reset Value 31:18 RO 0h 17:15 RW-O 010b RST/ PWR Description Reserved Uncore L1 Exit Latency (L1SELAT) This field indicates the length of time this Port requires to complete the transition from L1 to L0.
Processor Configuration Registers 2.12.20 LCTL—Link Control Register This register allows control of PCI Express link. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value 15:10 RO 0h Reserved Hardware Autonomous Width Disable (HAWD) When set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width.
Processor Configuration Registers 2.12.21 LSTS—DMI Link Status Register This register indicates DMI status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/DMIBAR 8A–8Bh 0001h RO-V 16 bits 00h Bit Attr Reset Value 15:12 RO 0h Reserved Link Training (TXTRN) When set, this bit indicates that the Physical Layer TXTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun.
Processor Configuration Registers 2.12.22 LCTL2—Link Control 2 Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/DMIBAR 98–99h 0002h RWS, RWS-V 16 bits 0h Bit Attr Reset Value 15:13 RO 0h Reserved 0b Powerg ood Compliance De-emphasis (ComplianceDeemphasis) This bit sets the de-emphasis level in Polling. Compliance state if the entry occurred due to the Enter Compliance bit being 1b. 1 = -3.5 dB 0 = -6 dB When the Link is operating at 2.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr 0/0/0/DMIBAR 98–99h 0002h RWS, RWS-V 16 bits 0h Reset Value RST/ PWR Powerg ood 6 5 4 3:0 Datasheet, Volume 2 RWS RWS RWS RWS Description 0b Selectable De-emphasis (selectabledeemphasis) When the Link is operating at 5 GT/s speed, this bit selects the level of de-emphasis. Encodings: 1 = -3.5 dB 0 = -6 dB When the Link is operating at 2.
Processor Configuration Registers 2.12.23 LSTS2—Link Status 2 Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value 15:1 RO 0h Reserved 0b Current De-emphasis Level (CURDELVL) When the Link is operating at 5 GT/s speed, this reflects the level of de-emphasis. 1 = -3.5 dB 0 = -6 dB When the Link is operating at 2.5 GT/s speed, this bit is 0b. 0 2.12.
Processor Configuration Registers 2.13 MCHBAR Registers in Memory Controller – Channel 0 Table 2-15 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-15. MCHBAR Registers in Memory Controller – Channel 0 Register Address Map Address Offset 2.13.
Processor Configuration Registers 2.13.2 TC_RAP_C0—Timing of DDR Regular Access Parameters Register This register provides the regular timing parameters in DCLK cycles. B/D/F/Type Address Offset: Reset Value: Access: Size: 2.13.3 0/0/0/MCHBAR MC0 4004–4007h 0010_4044h RW-L 32 bits Bit Attr Reset Value RST/ PWR 31:24 RO 0h 23:16 RW-L 10h 15:12 RW-L 4h Delay Internal WR to RD Transaction This field provides the delay from internal WR transaction to internal RD transaction.
Processor Configuration Registers 2.13.4 TC_SRFTP_C0—Self-Refresh Timing Parameters Register This register provides Self-refresh timing parameters. B/D/F/Type Address Offset: Reset Value: Access: Size: 2.13.5 0/0/0/MCHBAR MC0 42A4–42A7h 0000_B000h RW-L 32 bits Bit Attr Reset Value RST/ PWR 31:16 RO 0h Reserved 15:12 RW-L Bh Delay From SR Exit to First DDR Command tXS = tRFC+10ns. Setup of tXS_offset is # of cycles for 10 ns.
Processor Configuration Registers 2.13.6 TC_RFP_C0—Refresh Parameters Register B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default: 2.13.7 Bit Attr Reset Value 31:18 RO 0h RST/ PWR Description Reserved 17:16 RW-L 00b Uncore Double Refresh Control (DOUBLE_REFRESH_CONTROL) This field will allow the double self refresh enable/disable. 00b = Double refresh rate when DRAM is WARM/HOT. 01b = Force double self refresh regardless of temperature.
Processor Configuration Registers 2.14 MCHBAR Registers in Memory Controller – Channel 1 Table 2-16 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-16. MCHBAR Registers in Memory Controller – Channel 1 Register Address Map Address Offset 2.14.
Processor Configuration Registers 2.14.2 TC_RAP_C1—Timing of DDR Regular Access Parameters Register This register provides the regular timing parameters in DCLK cycles. B/D/F/Type Address Offset: Reset Value: Access: Size: Bit Attr Reset Value 31:24 RO 0h 23:16 RW-L 10h 15:12 RW-L 4h Delay Internal WR to RD Transaction This field provides the delay from internal WR transaction to internal RD transaction. The minimum delay is 4 DCLK cycles, whereas the maximum delay is 8 DCLK cycles.
Processor Configuration Registers 2.14.4 TC_SRFTP_C1—Self-Refresh Timing Parameters Register This register provides Self-refresh timing parameters. B/D/F/Type Address Offset: Reset Value: Access: Size: 2.14.5 0/0/0/MCHBAR MC1 46A4–46A7h 0000_B000h RW-L 32 bits Bit Attr Reset Value 31:16 RO 0 15:12 RW-L Bh 11:0 RO 0 RST/ PWR Description Reserved Delay From SR Exit to First DDR Command tXS = tRFC+10ns. Setup of tXS_offset is # of cycles for 10 ns.
Processor Configuration Registers 2.14.6 TC_RFP_C1—Refresh Parameters Register B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default: 2.14.7 Bit Attr Reset Value 31:18 RO 0h RST/ PWR Description Reserved 17:16 RW-L 00b Uncore Double Refresh Control (DOUBLE_REFRESH_CONTROL) This field will allow the double self refresh enable/disable. 00b = Double refresh rate when DRAM is WARM/HOT. 01b = Force double self refresh regardless of temperature.
Processor Configuration Registers 2.15 MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub (IMPH) Table 2-17 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-17. MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub Address Offset 2.15.
Processor Configuration Registers 2.16 MCHBAR Registers in Memory Controller – Common Table 2-18 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-18. MCHBAR Registers in Memory Controller – Common Register Address Map Address Offset 2.16.
Processor Configuration Registers 2.16.2 MAD_DIMM_ch0—Address Decode Channel 0 Register This register defines channel characteristics—number of DIMMs, number of ranks, size, interleave options.
Processor Configuration Registers 2.16.
Processor Configuration Registers 2.16.4 PM_SREF_config—Self Refresh Configuration Register This self refresh mode control register defines if and when DDR can go into SR. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/MCHBAR_MCMAIN 5060–5063h 0001_00FFh RW-L 32 bits 0000h Bit Attr Reset Value 31:15 RO 0h 16 RW-L 1 15:0 Datasheet, Volume 2 RW-L 00FFh RST/ PWR Description Reserved Uncore Self-refresh Enable This control bit is an INTEL RESERVED register.
Processor Configuration Registers 2.17 Memory Controller MMIO Registers Broadcast Group Table 2-19 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-19. Memory Controller MMIO Registers Broadcast Group Register Address Map Address Offset 2.17.
Processor Configuration Registers 2.17.2 PM_CMD_PWR—Power Management Command Power Register This register defines the power contribution of each command - ACT+PRE, CAS-read and CAS write. Assumption is that the ACT is always followed by a PRE (although not immediately), and REF commands are issued in a fixed rate and there is no need to count them. The register has three 8-bit fields.
Processor Configuration Registers 2.18 Integrated Graphics VT-d Remapping Engine Registers Table 2-20 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-20.
Processor Configuration Registers Table 2-20. Integrated Graphics VT-d Remapping Engine Register Address Map (Sheet 2 of 2) 2.18.
Processor Configuration Registers 2.18.2 CAP_REG—Capability Register This register reports general remapping hardware capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value 63:56 RO 0h 55 RO 1b Uncore DMA Read Draining (DRD) 0 = Hardware does not support draining of DMA read requests. 1 = Hardware supports draining of DMA read requests.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 23 22 Attr RO RO 0/0/0/GFXVTBAR 8–Fh 00C0_0000_20E6_0262h RO 64 bits 000h Reset Value 1b 1b 21:16 RO 100110b 15:13 RO 0h 12:8 Datasheet, Volume 2 RO 00010b RST/ PWR Description Uncore Isochrony (ISOCH) 0 = Remapping hardware unit has no critical isochronous requesters in its scope. 1 = Remapping hardware unit has one or more critical isochronous requesters in its scope.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description 7 RO 0b Uncore Caching Mode (CM) 0 = Not-present and erroneous entries are not cached in any of the remapping caches. Invalidations are not required for modifications to individual not present or invalid entries.
Processor Configuration Registers 2.18.3 ECAP_REG—Extended Capability Register This register reports remapping hardware extended capabilities.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value RST/ PWR 1 RO-V 1b Uncore Queued Invalidation Support (QI) 0 = Hardware does Not support queued invalidations. 1 = Hardware supports queued invalidations. Uncore Coherency (C) This field indicates if hardware access to the root, context, pagetable and interrupt-remap structures are coherent (snooped) or not.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 30 29 28 Datasheet, Volume 2 Attr WO RO RO 0/0/0/GFXVTBAR 18–1Bh 0000_0000h RO, WO 32 bits 000000h Reset Value 0b 0b 0b RST/ PWR Description Uncore Set Root Table Pointer (SRTP) Software sets this field to set/update the root-entry table pointer used by hardware. The root-entry table pointer is specified through the Root-entry Table Address (RTA_REG) register.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 27 26 25 228 Attr RO WO WO 0/0/0/GFXVTBAR 18–1Bh 0000_0000h RO, WO 32 bits 000000h Reset Value 0b 0b 0b RST/ PWR Description Uncore Write Buffer Flush (WBF) This bit is valid only for implementations requiring write buffer flushing. Software sets this field to request that hardware flush the RootComplex internal write buffers.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 24 Datasheet, Volume 2 Attr WO 0/0/0/GFXVTBAR 18–1Bh 0000_0000h RO, WO 32 bits 000000h Reset Value 0b 23 WO 0b 22:0 RO 0h RST/ PWR Description Uncore Set Interrupt Remap Table Pointer (SIRTP) This field is valid only for implementations supporting interruptremapping. Software sets this field to set/update the interrupt remapping table pointer used by hardware.
Processor Configuration Registers 2.18.5 GSTS_REG—Global Status Register This register reports general remapping hardware status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 31 30 29 28 RO-V RO-V RO RO Reset Value 0b 0b 0b 0b RST/ PWR Description Uncore Translation Enable Status (TES) This field indicates the status of DMA-remapping hardware.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.18.6 Attr 0/0/0/GFXVTBAR 1C–1Fh 0000_0000h RO, RO-V 32 bits 000000h Reset Value 23 RO-V 0b 22:0 RO 0h RST/ PWR Description Uncore Compatibility Format Interrupt Status (CFIS) This field indicates the status of Compatibility format interrupts on Intel 64 implementations supporting interrupt-remapping.
Processor Configuration Registers 2.18.7 CCMD_REG—Context Command Register This register manages context cache. The act of writing the upper most byte of the CCMD_REG with the ICC field set causes the hardware to perform the context-cache invalidation.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr 0/0/0/GFXVTBAR 28–2Fh 0800_0000_0000_0000h RW, RW-V, RO-V 64 bits 000000000h Reset Value RST/ PWR Description Uncore Context Actual Invalidation Granularity (CAIG) Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field).
Processor Configuration Registers 2.18.8 FSTS_REG—Fault Status Register This register indicates the various error status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value 31:16 RO 0h RST/ PWR Description Reserved Powerg ood Fault Record Index (FRI) This field is valid only when the PPF field is set.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 1 0 Datasheet, Volume 2 Attr ROS-V RW1CS 0/0/0/GFXVTBAR 34–37h 0000_0000h RO, ROS-V, RW1CS 32 bits 00000h Reset Value RST/ PWR Description 0b Powerg ood Primary Pending Fault (PPF) This bit indicates if there are one or more pending faults logged in the fault recording registers.
Processor Configuration Registers 2.18.9 FECTL_REG—Fault Event Control Register This register specifies the fault event interrupt message control bits. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 31 236 Attr RW 0/0/0/GFXVTBAR 38–3Bh 8000_0000h RW, RO-V 32 bits 00000000h Reset Value 1b 30 RO-V 0h 29:0 RO 0h RST/ PWR Description Uncore Interrupt Mask (IM) 0 = No masking of interrupt.
Processor Configuration Registers 2.18.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 2.18.11 Attr 0/0/0/GFXVTBAR 3C–3Fh 0000_0000h RW 32 bits Reset Value RST/ PWR Description 31:16 RW 0000h Uncore Extended Interrupt Message Data (EIMD) This field is valid only for implementations supporting 32-bit interrupt data fields.
Processor Configuration Registers 2.18.13 AFLOG_REG—Advanced Fault Log Register This register specifies the base address of the memory-resident fault-log region. This register is treated as RsvdZ for implementations not supporting advanced translation fault logging (AFL field reported as 0 in the Capability register).
Processor Configuration Registers 2.18.14 PMEN_REG—Protected Memory Enable Register This register enables the DMA-protected memory regions setup through the PLMBASE, PLMLIMT, PHMBASE, PHMLIMIT registers. This register is always treated as RO for implementations not supporting protected memory regions (PLMR and PHMR fields reported as Clear in the Capability register). Protected memory regions may be used by software to securely initialize remapping structures in memory.
Processor Configuration Registers 2.18.15 PLMBASE_REG—Protected Low-Memory Base Register This register sets up the base address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.18.16 PLMLIMIT_REG—Protected Low-Memory Limit Register This register sets up the limit address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.18.17 PHMBASE_REG—Protected High-Memory Base Register This register sets up the base address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.18.18 PHMLIMIT_REG—Protected High-Memory Limit Register This register sets up the limit address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.18.19 IQH_REG—Invalidation Queue Head Register This register indicates the invalidation queue head. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.18.
Processor Configuration Registers 2.18.21 IQA_REG—Invalidation Queue Address Register This register configures the base address and size of the invalidation queue. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
Processor Configuration Registers 2.18.23 IECTL_REG—Invalidation Event Control Register This register specifies the invalidation event interrupt control bits. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
Processor Configuration Registers 2.18.24 IEDATA_REG—Invalidation Event Data Register This register specifies the Invalidation Event interrupt message data. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 2.18.
Processor Configuration Registers 2.18.26 IRTA_REG—Interrupt Remapping Table Address Register This register provides the base address of Interrupt remapping table. This register is treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not supported in the Extended Capability register.
Processor Configuration Registers 2.18.27 IVA_REG—Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register. This register is a write only register.
Processor Configuration Registers 2.18.28 IOTLB_REG—IOTLB Invalidate Register This register invalidates the IOTLB. The act of writing the upper byte of the IOTLB_REG with IVT bit set causes the hardware to perform the IOTLB invalidation.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr 0/0/0/GFXVTBAR 108–10Fh 0200_0000_0000_0000h RW-V, RW, RO-V 64 bits 0_0000_0000_0000h Reset Value RST/ PWR Description Uncore IOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion (by clearing the IVT field). The following are the encodings for this field.
Processor Configuration Registers 2.18.29 FRCDL_REG—Fault Recording Low Register This register records fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register. This register is relevant only for primary fault logging. This register is sticky and can be cleared only through power good reset or by software clearing the RW1C fields by writing a 1.
Processor Configuration Registers 2.18.30 FRCDH_REG—Fault Recording High Register This register records fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register. This register is relevant only for primary fault logging. This register is sticky and can be cleared only through power good reset or by software clearing the RW1C fields by writing a 1.
Processor Configuration Registers 2.18.31 VTPOLICY—DMA Remap Engine Policy Control Register This register contains all the policy bits related to the DMA remap engine.
Processor Configuration Registers 2.19 PCU MCHBAR Registers Table 2-21 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-21.
Processor Configuration Registers 2.19.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal Estimation Configuration Register This register contains configuration regarding VTS temperature estimation calculations that are done by PCODE.
Processor Configuration Registers 2.19.2 MEM_TRML_THRESHOLDS_CONFIG—Memory Thermal Thresholds Configuration Register This register describes the thresholds for the memory thermal management in the MC. • The warm threshold defines when self-refresh is at double rate. Throttling can also be applied at this threshold based on the configuration in the MC. • The hot threshold defines what the acceptable limit of the temperature is. When this threshold is crossed, severe throttling takes place.
Processor Configuration Registers 2.19.3 MEM_TRML_STATUS_REPORT—Memory Thermal Status Report Register This register reports the thermal status of DRAM.
Processor Configuration Registers 2.19.4 MEM_TRML_TEMPERATURE_REPORT—Memory Thermal Temperature Report Register This register is used to report the estimated thermal status of the memory. The Channel VTS estimated maximum temperature field is used to report the estimated maximum temperature of all ranks. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.19.
Processor Configuration Registers 2.19.6 GT_PERF_STATUS—GT Performance Status Register P-state encoding for the Secondary Power Plane's current PLL frequency and the current VID. B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 2.19.7 0/0/0/MCHBAR PCU 5948-594Bh 0000_0000h RO-V 32 bits 0000h Bit Attr Reset Value 31:16 RO 0h 15:8 RO-V 00h Uncore RP-State Ratio (RP_STATE_RATIO) Ratio of the current RP-state.
Processor Configuration Registers 2.19.8 SSKPD—Sticky Scratchpad Data Register This register holds 64 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit Reset Value RST/ PWR Description Self Refresh Latency Time (WM1) Number of microseconds to access memory if memory is in Self Refresh (0.5 us granularity). 00h = 0 us 01h = 0.5 us 02h = 1 us ... 3Fh = 31.5 us NOTE: The value in this field corresponds to the memory latency requested to the Display Engine when Memory is in Self Refresh.
Processor Configuration Registers 2.20 PXPEPBAR Registers Table 2-22 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-22. PXPEPBAR Register Address Map 2.20.
Processor Configuration Registers 2.21 Default PEG/DMI VT-d Remapping Engine Registers Table 2-23 lists the registers arranged by address offset. Register bit descriptions are in the sections following the table. Table 2-23.
Processor Configuration Registers Table 2-23. Default PEG/DMI VT-d Remapping Engine Register Address Map (Sheet 2 of 2) Address Offset Register Symbol A8–ABh IEADDR_REG AC–AFh IEUADDR_REG B0–B7h RSVD IRTA_REG C0–FFh RSVD IVA_REG 108–10Fh IOTLB_REG 110–1FFh RSVD 208–20Fh RSVD 210–FEFh RSVD FF0–FF3h 2.21.
Processor Configuration Registers 2.21.2 CAP_REG—Capability Register This register reports general remapping hardware capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value 63:56 RO 0h 55 RO 1b Uncore DMA Read Draining (DRD) 0 = Hardware does Not support draining of DMA read requests. 1 = Hardware supports draining of DMA read requests.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 23 22 Attr RO RO Reset Value 0b 1b 21:16 RO 100110b 15:13 RO 0h 12:8 Datasheet, Volume 2 RO 00010b 0/0/0/VC0PREMAP 8–Fh 00C9_0080_2066_0262h RO 64 bits 000h RST/ PWR Description Uncore Isochrony (ISOCH) 0 = Remapping hardware unit has no critical isochronous requesters in its scope. 1 = Remapping hardware unit has one or more critical isochronous requesters in its scope.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description 7 RO 0b Uncore Caching Mode (CM) 0 = Not-present and erroneous entries are Not cached in any of the remapping caches. Invalidations are not required for modifications to individual not present or invalid entries.
Processor Configuration Registers 2.21.3 ECAP_REG—Extended Capability Register This register reports remapping hardware extended capabilities.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value RST/ PWR 1 RO-V 1b Uncore Queued Invalidation Support (QI) 0 = Hardware does not support queued invalidations. 1 = Hardware supports queued invalidations. Uncore Coherency (C) This field indicates if hardware access to the root, context, pagetable and interrupt-remap structures are coherent (snooped) or not.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 30 29 28 Datasheet, Volume 2 Attr WO RO RO 0/0/0/VC0PREMAP 18–1Bh 0000_0000h WO, RO 32 bits 00_0000h Reset Value 0b 0b 0b RST/ PWR Description Uncore Set Root Table Pointer (SRTP) Software sets this field to set/update the root-entry table pointer used by hardware. The root-entry table pointer is specified through the Root-entry Table Address (RTA_REG) register.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 27 26 25 272 Attr RO WO WO 0/0/0/VC0PREMAP 18–1Bh 0000_0000h WO, RO 32 bits 00_0000h Reset Value 0b 0b 0b RST/ PWR Description Uncore Write Buffer Flush (WBF) This bit is valid only for implementations requiring write buffer flushing. Software sets this field to request that hardware flush the RootComplex internal write buffers.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 24 Datasheet, Volume 2 Attr WO 0/0/0/VC0PREMAP 18–1Bh 0000_0000h WO, RO 32 bits 00_0000h Reset Value 0b 23 WO 0b 22:0 RO 0h RST/ PWR Description Uncore Set Interrupt Remap Table Pointer (SIRTP) This field is valid only for implementations supporting interruptremapping. Software sets this field to set/update the interrupt remapping table pointer used by hardware.
Processor Configuration Registers 2.21.5 GSTS_REG—Global Status Register This register reports general remapping hardware status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 31 30 29 28 RO-V RO-V RO RO Reset Value 0b 0b 0b 0b RST/ PWR Description Uncore Translation Enable Status (TES) This bit indicates the status of DMA-remapping hardware.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.21.6 Attr 0/0/0/VC0PREMAP 1C–1Fh 0000_0000h RO, RO-V 32 bits 00_0000h Reset Value 23 RO-V 0b 22:0 RO 0h RST/ PWR Description Uncore Compatibility Format Interrupt Status (CFIS) This field indicates the status of Compatibility format interrupts on Intel 64 implementations supporting interrupt-remapping.
Processor Configuration Registers 2.21.7 CCMD_REG—Context Command Register This register manages context cache. The act of writing the upper most byte of the CCMD_REG with the ICC field set causes the hardware to perform the context-cache invalidation.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr 0/0/0/VC0PREMAP 28–2Fh 0000_0000_0000_0000h RW-V, RW, RO-V 64 bits 0_0000_0000h Reset Value RST/ PWR Description Uncore Context Actual Invalidation Granularity (CAIG) Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field).
Processor Configuration Registers 2.21.8 FSTS_REG—Fault Status Register This register indicates the various error status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr Reset Value 31:16 RO 0h RST/ PWR Description Reserved Powerg ood Fault Record Index (FRI) This field is valid only when the PPF field is Set.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 1 0 Datasheet, Volume 2 Attr ROS-V RW1CS 0/0/0/VC0PREMAP 34–37h 0000_0000h RW1CS, ROS-V, RO 32 bits 0_0000h Reset Value RST/ PWR Description 0b Powerg ood Primary Pending Fault (PPF) This field indicates if there are one or more pending faults logged in the fault recording registers.
Processor Configuration Registers 2.21.9 FECTL_REG—Fault Event Control Register This register specifies the fault event interrupt message control bits. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 31 280 Attr RW 0/0/0/VC0PREMAP 38-3Bh 8000_0000h RW, RO-V 32 bits 0000_0000h Reset Value 1b 30 RO-V 0h 29:0 RO 0h RST/ PWR Description Uncore Interrupt Mask (IM) 0 = No masking of interrupt.
Processor Configuration Registers 2.21.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 2.21.11 Attr 0/0/0/VC0PREMAP 3C–3Fh 0000_0000h RW 32 bits Reset Value RST/ PWR Description 31:16 RW 0000h Uncore Extended Interrupt Message Data (EIMD) This field is valid only for implementations supporting 32-bit interrupt data fields.
Processor Configuration Registers 2.21.13 AFLOG_REG—Advanced Fault Log Register This register specifies the base address of the memory-resident fault-log region. This register is treated as RsvdZ for implementations not supporting advanced translation fault logging (AFL field reported as 0 in the Capability register).
Processor Configuration Registers 2.21.14 PMEN_REG—Protected Memory Enable Register This register enables the DMA-protected memory regions setup through the PLMBASE, PLMLIMT, PHMBASE, PHMLIMIT registers. This register is always treated as RO for implementations not supporting protected memory regions (PLMR and PHMR fields reported as Clear in the Capability register). Protected memory regions may be used by software to securely initialize remapping structures in memory.
Processor Configuration Registers 2.21.15 PLMBASE_REG—Protected Low-Memory Base Register This register sets up the base address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.21.16 PLMLIMIT_REG—Protected Low-Memory Limit Register This register sets up the limit address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.21.17 PHMBASE_REG—Protected High-Memory Base Register This register sets up the base address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.21.18 PHMLIMIT_REG—Protected High-Memory Limit Register This register sets up the limit address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.21.19 IQH_REG—Invalidation Queue Head Register Register indicating the invalidation queue head. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.21.
Processor Configuration Registers 2.21.21 IQA_REG—Invalidation Queue Address Register This register configures the base address and size of the invalidation queue. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
Processor Configuration Registers 2.21.23 IECTL_REG—Invalidation Event Control Register This register specifies the invalidation event interrupt control bits. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
Processor Configuration Registers 2.21.24 IEDATA_REG—Invalidation Event Data Register This register specifies the Invalidation Event interrupt message data. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 2.21.
Processor Configuration Registers 2.21.26 IEUADDR_REG—Invalidation Event Upper Address Register This register specifies the Invalidation Event interrupt message upper address. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 31:0 2.21.
Processor Configuration Registers 2.21.28 IVA_REG—Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register. This register is a write only register.
Processor Configuration Registers 2.21.29 IOTLB_REG—IOTLB Invalidate Register Register to invalidate IOTLB. The act of writing the upper byte of the IOTLB_REG with IVT field Set causes the hardware to perform the IOTLB invalidation.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Attr 0/0/0/VC0PREMAP 108–10Fh 0000_0000_0000_0000h RW, RO-V, RW-V 64 bits 0_0000_0000_0000h Reset Value RST/ PWR Description Uncore IOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion (by clearing the IVT field).
Processor Configuration Registers 296 Datasheet, Volume 2
