Datasheet

Processor Configuration Registers
198 Datasheet, Volume 2
2.12.17 DMILE2D—DMI Link Entry 2 Description Register
This register provides the first part of a Link Entry that declares an internal link to
another Root Complex Element.
2.12.18 DMILE2A—DMI Link Entry 2 Address Register
This register provides the second part of a Link Entry that declares an internal link to
another Root Complex Element.
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 60–63h
Reset Value: 0000_0000h
Access: RO, RW-O
Size: 32 bits
BIOS Optimal Default 0000h
Bit Attr
Reset
Value
RST/
PWR
Description
31:24 RO 00h Uncore
Target Port Number (TPN)
This field specifies the port number associated with the element
targeted by this link entry (Egress Port). The target port number is
with respect to the component that contains this element as
specified by the target component ID.
23:16 RW-O 00h Uncore
Target Component ID (TCID)
This field identifies the physical or logical component that is
targeted by this link entry.
BIOS Requirement: Must be initialized according to guidelines in
the PCI Express* Isochronous/Virtual Channel Support Hardware
Programming Specification (HPS).
15:2 RO 0h Reserved
1RO 0bUncore
Link Type (TXTYP)
This bit indicates that the link points to memory-mapped space (for
RCRB).
The link address specifies the 64-bit base address of the target
RCRB.
0RW-O 0bUncore
Link Valid (LV)
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 68–6Bh
Reset Value: 0000_0000h
Access: RW-O
Size: 32 bits
BIOS Optimal Default 000h
Bit Attr
Reset
Value
RST/
PWR
Description
31:12 RW-O 00000h Uncore
Link Address (LA)
Memory mapped base address of the RCRB that is the target
element (Egress Port) for this link entry.
11:0 RO 0h Reserved