Datasheet

Datasheet, Volume 2 263
Processor Configuration Registers
2.20 PXPEPBAR Registers
Table 2-22 lists the registers arranged by address offset. Register bit descriptions are in
the sections following the table.
2.20.1 EPVC0RCTL—EP VC 0 Resource Control Register
This register controls the resources associated with Egress Port Virtual Channel 0.
Table 2-22. PXPEPBAR Register Address Map
Address
Offset
Register
Symbol
Register Name Reset Value Access
0–13h RSVD Reserved 0h RO
14–17h EPVC0RCTL EP VC 0 Resource Control 8000_00FFh RO, RW
18–9F RSVD Reserved — —
B/D/F/Type: 0/0/0/PXPEPBAR
Address Offset: 14–17h
Reset Value: 8000_00FFh
Access: RO, RW
Size: 32 bits
BIOS Optimal Default 00000h
Bit Attr
Reset
Value
RST/
PWR
Description
31:20 RO 0h Reserved
19:17 RW 000b Uncore
Port Arbitration Select (PAS)
This field configures the VC resource to provide a particular Port
Arbitration service. The value of 0h corresponds to the bit position
of the only asserted bit in the Port Arbitration Capability field.
16:0 RO 0h Reserved