Datasheet

Processor Configuration Registers
94 Datasheet, Volume 2
2.6.14 SSTS1—Secondary Status Register
SSTS is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI
bridge embedded within the processor.
B/D/F/Type: 0/1/0–2/PCI
Address Offset: 1E–1Fh
Reset Value: 0000h
Access: RW1C, RO
Size: 16 bits
BIOS Optimal Default 00h
Bit Attr
Reset
Value
RST/
PWR
Description
15 RW1C 0b Uncore
Detected Parity Error (DPE)
This bit is set by the Secondary Side for a Type 1 Configuration
Space header device whenever it receives a Poisoned TLP,
regardless of the state of the Parity Error Response Enable bit in
the Bridge Control Register.
14 RW1C 0b Uncore
Received System Error (RSE)
This bit is set when the Secondary Side for a Type 1 configuration
space header device receives an ERR_FATAL or ERR_NONFATAL.
13 RW1C 0b Uncore
Received Master Abort (RMA)
This bit is set when the Secondary Side for Type 1 Configuration
Space Header Device (for requests initiated by the Type 1 Header
Device itself) receives a Completion with Unsupported Request
Completion Status.
12 RW1C 0b Uncore
Received Target Abort (RTA)
This bit is set when the Secondary Side for Type 1 Configuration
Space Header Device (for requests initiated by the Type 1 Header
Device itself) receives a Completion with Completer Abort
Completion Status.
11 RO 0b Uncore
Signaled Target Abort (STA)
Not Applicable or Implemented. Hardwired to 0. The processor
does not generate Target Aborts (The root port will never complete
a request using the Completer Abort Completion status).
UR detected inside the processor (such as in /MC will be reported
in primary side status)
10:9 RO 00b Uncore
DEVSELB Timing (DEVT)
Not Applicable or Implemented. Hardwired to 0.
8RW1C 0b Uncore
Master Data Parity Error (SMDPE)
When set, this bit indicates that the processor received across the
link (upstream) a Read Data Completion Poisoned TLP (EP=1). This
bit can only be set when the Parity Error Enable bit in the Bridge
Control register is set.
7RO 0bUncore
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0.
6RO 0h Reserved
5RO 0bUncore
66/60 MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0.
4:0 RO 0h Reserved