Specifications

Errata
44 Intel
®
Core
™
2 Duo Processor
Specification Update
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AW71. The XRSTOR Instruction May Fail to Cause a General-Protection
Exception
Problem: The XFEATURE_ENABLED_MASK register (XCR0) bits [63:9] are reserved and
must be 0; consequently, the XRSTOR instruction should cause a general-
protection exception if any of the corresponding bits in the XSTATE_BV field
in the header of the XSAVE/XRSTOR area is set to 1. Due to this erratum, a
logical processor may fail to cause such an exception if one or more of these
reserved bits are set to 1.
Implication: Software may not operate correctly if it relies on the XRSTOR instruction to
cause a general-protection exception when any of the bits [63:9] in the
XSTATE_BV field in the header of the XSAVE/XRSTOR area is set to 1.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AW72. The XSAVE Instruction May Erroneously Modify Reserved Bits in the
XSTATE_BV Field
Problem: Bits 63:2 of the HEADER.XSTATE_BV are reserved and must be 0. Due to this
erratum, the XSAVE instruction may erroneously modify one or more of these
bits.
Implication: If one of bits 63:2 of the XSTATE_BV field in the header of the
XSAVE/XRSTOR area had been 1 and was then cleared by the XSAVE
instruction, a subsequent execution of XRSTOR may not generate the #GP
(general-protection exception) that would have occurred in the absence of
this erratum. Alternatively, if one of those bits had been 0 and was then set
by the XSAVE instruction, a subsequent execution of XRSTOR may generate a
#GP that would not have occurred in the absence of this erratum.
Workaround: It is possible for the BIOS to contain a partial workaround for this erratum
that prevents XSAVE from setting HEADER.XSTATE_BV reserved bits. To
ensure compatibility with future processors, software should not set any
XSTATE_BV reserved bits when configuring the header of the XSAVE/XRSTOR
save area.
Status: For the steppings affected, see the Summary Tables of Changes.
AW73. Store Ordering Violation When Using XSAVE
Problem: The store operations done as part of the XSAVE instruction may cause a store
ordering violation with older store operations. The store operations done to
save the processor context in the XSAVE instruction flow , when XSAVE is
used to store only the SSE context, may appear to execute before the
completion of older store operations.