NuDAQ / NuIPC PCI-7200 / cPCI-7200 12MB/S High Speed Digital Input/ Output Card User’s Guide Recycled Paper
©Copyright 1999~2000 ADLINK Technology Inc. All Rights Reserved. Manual Rev. 2.20: October 14, 2000 The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer.
Getting service from ADLINK Customer Satisfaction is always the most important thing for ADLINK Tech Inc. If you need any help or service, please contact us and get it. ADLINK Technology Inc. Web Site http://www.adlink.com.tw http://www.adlinktechnology.com Sales & Service service@adlink.com.tw NuDAQ nudaq@ adlink.com.tw NuDAM nudam@ adlink.com.tw Technical NuIPC nuipc@ adlink.com.tw Support NuPRO nupro@ adlink.com.tw Software sw@ adlink.com.tw TEL +886-2-82265877 FAX +886-2-82265717 Address 9F, No.
Table of Contents Chapter 1 Introduction............................................................. 1 1.1 1.2 1.3 1.4 Applications.................................................................... 1 Features.......................................................................... 2 Specifications ................................................................. 2 Software Supporting....................................................... 4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.4.
Chapter 5 C/C++ Libraries ....................................................30 5.1 5.2 Libraries Installation..................................................... 30 Programming Guide...................................................... 31 5.2.1 5.2.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 Naming Convention ...................................................................31 Data Types.................................
How to Use This Guide This manual is designed to help you use the PCI-7200 and cPCI-7200. The functionality of PCI-7200 and cPCI-7200 are the same except that cPCI-7200 has 4 auxiliary digital input and output. Therefore, the “PCI-7200” represents both PCI-7200 and cPCI-7200 if not specified. The manual describes how to modify various settings on the PCI-7200 card to meet your requirements.
1 Introduction The PCI-7200/cPCI-7200 is PCI/CompactPCI form factor high-speed digital I/O card, it consists of 32 digital input channels, and 32 digital output channels. High performance designs and the state-of-the-art technology make this card suitable for high-speed digital input and output applications. The PCI-7200 performs high-speed data transfers using bus -mastering DMA via 32-bit PCI bus architecture. The maximum data transfer rates can be up to 12MB per second.
1.
l Input Voltage: Low: Min. 0V; Max. 0.8V High: Min. +2.0V l Input Load: Low: +0.5V @ -0.6mA max. High: +2.7V @+20µA max. l Output Voltage: Low: Min. 0V; Max. 0.5V High: Min. +2.7V l Driving Capacity: Low: Max. +0.5V at 24mA (Sink) High: Min. 2.4V at -3.0mA (Source) u Programmable Counter l Device: 82C54-10, with a 4MHz time base l Timer 0: DI clock source l Timer 1: DO clock source l Timer2: Base clock of Timer #0 and Timer #1 l Pacer Output: 0.
1.4 Software Supporting ADLink provides versatile software drivers and packages for users’ different approach to built-up a system. We not only provide programming library such as DLL for many Windows systems, but also provide drivers for many software ® TM TM TM TM package such as LabVIEW , HP VEE , DASYLab , InTouch , InControl , TM ISaGRAF , and so on. All the software options are included in the ADLink CD. The non-free software drivers are protected with serial licensed code.
® 1.4.2 PCIS-LVIEW: LabVIEW Driver ® PCIS-LVIEW contains the VIs, which are used to interface with NI’s LabVIEW software package. The PCIS-LVIEW supports Windows 95/98/NT/2000. The ® LabVIEW drivers are free shipped with the board. You can install and use them without license. For detail information about PCIS-LVIEW, please refer to the user’s guide in the CD. (\\Manual_PDF\Software\PCIS-LVIEW) 1.4.
1.4.7 PCIS-ISG: ISaGRAF TM driver The ISaGRAF WorkBench is an IEC1131-3 SoftPLC control program development environment. The PCIS-ISG includes ADLink products’ target drivers for ISaGRAF under Windows NT environment. The PCIS-ISG is included in the ADLINK CD. It needs license. TM 1.4.8 PCIS-ICL: InControl Driver PCIS-ICL is the InControl driver which support the Windows NT. PCIS-ICL is included in the ADLINK CD. It needs license. The 1.4.
2 Installation This chapter describes how to install the PCI-7200. At first, the content of the package and the unpacking information that you should be careful are described. Because the PCI-7200 is a plug and play device, there is no more jumper or DIP switch setting for configuration. The Interrupt number and I/O port address are assigned by the system BIOS during system boot up. 2.
2.2 Unpacking Your PCI-7200 card contains sensitive electronic components that can be easily damaged by static electricity. The card should be done on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the card module carton for obvious damage. Shipping and handling may cause damage to your module. Be sure there are no shipping and handling damages on the module before processing.
CN2 PCI-7200 Rev A1 PCI -Bus Controller ALTERA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CN1 2.4 cPCI/PCI-7200’s Layout Figure 2.
Figure 2.
2.5 Hardware Installation Outline Hardware configuration The PCI cards (or CompactPCI cards) are equipped with plug and play PCI controller, it can request base addresses and interrupt according to PCI standard. The system BIOS will install the system resource based on the PCI cards’ configuration registers and system parameters (which are set by system BIOS). Interrupt assignment and memory usage (I/O port locations) of the PCI cards can be assigned by system BIOS only.
2.6 Connector Pin Assignments 2.6.1 PCI-7200 Pin Assignments The PCI-7200 comes equipped with one 37-pin D-Sub connector (CN2) located on the rear mounting plate and one 40-pin female flat cable header connector (CN1). The CN2 is located on the rear mounting plate; the CN1 is on front of the board. Refer section 2.2 PCI-7200‘s layout.
DI 0 DI 1 DI 2 DI 3 DI 4 DI 5 DI 6 DI 7 DI 8 DI 9 DI10 DI11 DI12 DI13 DI14 DI15 +5V I_ACK I_REQ 1 20 2 21 3 4 5 22 23 24 6 25 7 26 8 9 10 11 12 13 27 28 29 30 31 32 14 15 33 34 16 17 35 36 18 19 37 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 DO13 DO14 DO15 GND I_TRG Figure 2.
2.6.
2.7 8254 for Timer Pacer Generation 8254 Timer/Counter CLK0 GATE0 “H” “H” CLK1 GATE1 4MHz Clock Timer 0 OUT0 Digital Input Timer Pacer OUT1 Digital Output Timer Pacer Timer 1 Timer 2 CLK2 GATE2 “H” OUT2 Figure 2.4 8254 configuration The internal timer/counter 8254 on the PCI-7200 is configured as above diagram (figure 2.4). User can use it to generate the timer pacer for both digital input and digital output trigger.
3 Registers Format 3.1 I/O Registers Format The PCI-7200 occupies 8 consecutive 32-bit I/O addresses in the PC I/O address space and the cPCI-7200 occupies 9 consecutive 32-bit I/O addresses. Table 4.1 shows the I/O Map Address Base + 0 Base + 4 Base + 8 Base + C Base + 10 Base + 14 Base + 18 Base + 1C Base + 20 (cPCI-7200 only) Caution: Read Counter 0 Counter 1 Counter 2 --Digital Input Reg.
3.2 Digital Input Register (BASE + 10) 32 digital input channels can be read from this register Address: BASE + 10 Attribute: READ Only Data Format: Byte Base +10 Base +11 Base +12 Base +13 7 DI7 DI15 DI23 DI31 6 DI6 DI14 DI22 DI30 5 DI5 DI13 DI21 DI29 4 DI4 DI12 DI20 DI28 3 DI3 DI11 DI19 DI27 2 DI2 DI10 DI18 DI26 1 DI1 DI9 DI17 DI25 0 DI0 DI8 DI16 DI24 3.
u Digital Input Mode Setting: I_ACK: Input ACK Enable 1: Input ACK is enabled (input ACK will be asserted after input data is read by CPU or written to input FIFO) 0: Input ACK is disabled I_REQ: Input REQ Strobe Enabled 1: Use I_REQ edge to latch input data 0: I_REQ is disabled I_TIME0: Input Timer 0 Enable 1: Input is sampled by falling edge of Counter 0 output (COUT0) 0: Input Timer 0 is disabled I_FIFO: Input FIFO Enable Mode 1: Input FIFO is enabled (input data is saved to input FIFO) 0: Input FIFO is
O_TRG: Digital Output Trigger Signal This bit is used to control the O_TRG output of PCI-7200, the signal is on CN1 pin 36 of PCI-7200 or CN1 pin 26 of cPCI-7200 when 1: O_TRG 1 goes High (1) 0: O_TRG 1 goes Low (0) u Digital I/O FIFO Status: I_OVR: Input data overrun 1: Digital Input FIFO is full (overrun) during input data transfer 0: No input data overrun occurred Input data overrun occurred, the I_OVR bit is set when input FIFO is full and there is new input data coming in.
T0_EN: Interrupt is triggered by timer 0 output. 1: Timer 0 interrupt is enabled 0: Timer 0 interrupt is disabled T1_EN: Interrupt is triggered by timer 1 output. 1: Timer 1 interrupt is enabled 0: Timer 1 interrupt is disabled T2_EN: Interrupt is triggered by timer 2 output.
T1_T2: Timer 1 is cascaded with timer 2 1: Timer 1 and timer 2 are cascaded together, output of timer 2 connects to the clock input of timer 1. 0: Not cascaded, the 4 MHz clock is connected to the timer 1 clock input. u I_REQ Polarity Selection: When the input sampling is controlled by the I_REQ signal only, the I_REQ can be programmed to be rising edge active or falling edge active.
3.6 8254 Timer Registers (BASE + 0) The 8254 timer/ counter IC occupies 4 I/O address. Users can refer to Tundra's or Intel's data sheet for a full description of the 8254 features. You can download the 8254 data sheet from the following web site: http://support.intel.com/support/controllers/peripheral/231164.htm or http://www.tundra.com (for Tundra’s 82C54 datasheet.
4 Operation Theorem In PCI-7200, there are four data transfer modes can be used for digital I/O access and control, these modes are: 1. Direct Program Control: the digital inputs and outputs can be read/written and controlled by its corresponding I/O port address directly. 2. Internal Timer Pacer Mode: the digital input and output operations are paced by internal timer pacer and transferred by bus mastering DMA. 3.
4.2 Timer Pacer Mode The digital I/O access control is clocked by timer pacer, which is generated by an interval programming timer/counter chip 8254. There are three timers on the 8254. The timer 0 is used to generate timer pacer for digital input, and timer 1 is used for digital output. The configuration is illustrated as below.
4.3 External Clock Mode The digital input is clocked by external strobe, which is from the Pin 19 (I_REQ) of CN2 (PCI-7200) or Pin 24 of CN1 (cPCI-7200). The operation sequence is very similar to Timer Pacer Trigger. The only difference is the clock source. 1. The external input strobe is generated from outside device, and go through the Pin 19 (I_REQ) of CN2 and to latch the digital input. 2. The digital input data are saved in FIFO after an I/O strobe signal is coming in. 3.
Digital Input DATA 1 2 IN_REQ Latch Digital Input or Digital Output IN_ACK 3 4 PC's Main Memory Digital Input FIFO Bus mastering DMA data Transfer 5 O_REQ & O_ACK for Digital Output 1. Digital Output Data is moved from PC memory to FIFO o f PCI-7200 by using DMA data mastering data transfer. 2. Move output data from FIFO to digital output circuit. 3. Output data is ready. 4. An O_REQ signal is generated and sent to outside device. 5. After an O_ACK is got, the step 2 to step 5 will be repeated again.
4.5 Timing Characteristic 1. I_REQ as input data strobe (Rising Edge Active) th tl IN_ I_REQ tcyc D10~DI31 valid data valid data ts tn th ≥ 60ns tI ≥ 60ns ts ≥ 2ns tn ≥ 30ns tCYC ≥ 5 PCI CLK Cycle 2.
3. I_REQ & I_ACK Handshaking t5 IN I_REQ t3 t4 IN I_ACK valid data D10~DI31 t1 valid data t2 t1 ≥ 0ns t5 ≥ 60ns t3 ≥ 2 PCI CLK Cycle t2 ≥ 0ns t4 ≥ 1 PCI CLK Cycle Note: I_REQ must be asserted until I_ACK asserts, I_ACK will be asserted until I_REQ de-asserts. 4.
5. O_REQ & O_ACK Handshaking t3 O_REQ OUT_REQ t2 OUT_ACK O_ACK valid data valid data DO0~Do31 t1 t1 19ns t2 1 PCI CLK Cycle t3 5 PCI CLK Cycle Note: O_ACK must be de-asserted before O_REQ asserts, O_ACK can be asserted any time after O_REQ asserts, O_REQ will be reasserted after O_ACK is asserted.
5 C/C++ Libraries This chapter describes the software library for operating this card. Only the functions in DOS library and Windows 95 DLL are described. Please refer to the PCIS-DASK function reference manual, which included in ADLINK CD, for the descriptions of the Windows 98/NT/2000 DLL functions. The function prototypes and some useful constants are defined in the header files LIB directory (DOS) and INCLUDE directory (Windows 95). For Windows 95 DLL, the developing environment can be Visual Basic 4.
5.2 Programming Guide 5.2.1 Naming Convention The functions of the NuDAQ PCI cards or NuIPC CompactPCI cards’ software driver are using full-names to represent the functions' real meaning. The naming convention rules are: In DOS Environment : _{hardware_model}_{action_name}. e.g. _7200_Initial(). All functions in PCI-7200 driver are with 7200 as {hardware_model}. But they can be used by PCI-7200, cPCI-7200.
5.3 _7200_Initial @ Description A PCI-7200 card is initialized according to the card number. Because the PCI-7200 is PCI bus architecture and meets the plug and play design, the IRQ and base_address ( pass-through address) are assigned by system BIOS directly. Every PCI-7200 card has to be initialized by this function before calling other functions. Note: Because configuration of PCI-7200 is handled by the system, there is no jumpers or DMA selection on the PCI boards that need to be set up by the users.
5.4 _7200_Switch_Card_No @ Description After initialized more than one PCI-7200 card, this function is used to select which card is used currently.
5.6 _7200_AUX_DI_Channel @ Description Read data from auxiliary digital input channel of cPCI-7200 card. There are 4 digital input channels on the cPCI-7200 auxiliary digital input port. When performs this function, the auxiliary digital input port is read and the value of the corresponding channel is returned. * channel means each bit of digital input port.
5.8 _7200_AUX_DO_Channel @ Description Write data to auxiliary digital output channel (bit). There are 4 auxiliary digital output channels on the cPCI-7200. When performs this function, the digital output data is written to the corresponding channel.
5.10 _7200_DI_Channel @ Description This function is used to read data from digital input channels (bit). There are 32 digital input channels on the PCI-7200. When performs this function, the digital input port is read and the value of the corresponding channel is returned. * channel means each bit of digital input port.
5.12 _7200_DO_Channel @ Description This function is used to write data to digital output channels (bit). There are 32 digital output channels on the PCI-7200. When performs this function, the digital output data is written to the corresponding channel.
5.13 _7200_Alloc_DMA_Mem @ Description Contact Windows 95/98 system to allocate a block of contiguous memory for single-buffered DMA transfer. This function is only available in Windows 95/98 version.
5.14 _7200_Free_DMA_Mem @ Description Release the system DMA memory under Windows 95/98 environment. This function is only available in Windows 95/98 version. @ Syntax Visual C++ (Windows 95) int W_7200_Free_DMA_Mem (U32 handle) Visual Basic (Windows 95) W_7200_Free_DMA_Mem (ByVal handle As Long ) As Long @ Argument handle: The handle of system DMA memory to release. @ Return Code ERR_NoError 5.
the actual size of allocated memory for each half of circular buffer. @ Return Code ERR_NoError ERR_SmallerDMAMemAllocated 5.16 _7200_Free_DBDMA_Mem @ Description Release a system circular buffer DMA memory under Windows 95/98 environment. This function is only available in Windows 95/98 version. For double-buffered transfer principle, please refer to Section 6 “Double Buffered Mode Principle”.
Bus Mastering DMA mode of PCI-7200 : PCI bus mastering offers the highest possible speed available on the PCI-7200. When the function _7200_DI_DMA_Start is executed, it will enable PCI bus master operation. This is conceptually similar to DMA (Direct Memory Access) transfers in a PC but is really PCI bus mastering. It does not use an 8237-style DMA controller in the host computer and therefore isn't blocked in 64K max. groups. PCI-7200 bus mastering works as follows: 1.
@ Syntax Visual C++ (Windows 95) int W_7200_DI_DMA_Start (U8 mode, U32 count, U32 handle, Boolean wait_trg, U8 trg_pol, Boolean clear_fifo, Boolean disable_di) Visual Basic (Windows 95) W_7200_DI_DMA_Start (ByVal mode As Byte, ByVal count As Long, ByVal handle As Long, ByVal wait_trg as Byte, ByVal trg_pol As Byte, ByVal clear_fifo As Byte, ByVal disable_di As Byte) As Long C/C++ (DOS) int _7200_DI_DMA_Start (U8 mode, U32 count, U32 *di_buffer, Boolean wait_trig, U8 trig_pol, Boolean clear_fifo, Boolean d
clear_fifo : 0: retain the FIFO data 1: clear FIFO data before perform digital input disable_di : 0: digital input operation still active after DMA transfer complete 1: disable digital input operation immediately when DMA transfer complete @ Return Code ERR_NoError ERR_BoardNoInit ERR_InvalidDIOMode ERR_InvalidDIOCnt ERR_NotDWordAlign ERR_DMATransferNotAllowed 5.
5.19 _7200_DI_DMA_Stop @ Description This function is used to stop the DMA data transferring. After executing this function, the _7200_DI_DMA_Start function is stopped. The function returns the number of the data which has been transferred, no matter if the digital input DMA data transfer is stopped by this function or by the DMA terminal count ISR.
5.21 _7200_CheckHalfReady @ Description When you use _7200_DI_DMA_Start to sample digital input data and double buffer mode is set as enable. You must use _7200_CheckHalfReady to check data ready (data half full) or not in the circular buffer, and using _7200_DblBufferTransfer to get data.
5.23 _7200_GetOverrunStatus @ Description When you use _7200_DI_DMA_Start to convert Digital I/O data with double buffer mode enabled, and if you do not use _7200_DblBufferTransfer to move converted data then the double buffer overrun will occur, using this function to check overrun count.
C/C++ (DOS) int _7200_DO_DMA_Start (U8 mode, U32 count, U32 *do_buffer, Boolean repeat) @ Argument mode : Digital output trigger modes DO_MODE_0 : Internal timer pacer (TIME 1) DO_MODE_1 : Internal timer pacer with O_REQ enable DO_MODE_2 : O_REQ & I_REQ handshaking count : the sample number of digital output data (in samples, not in bytes!) handle (Win 95): the handle of system DMA memory.
C/C++ (DOS) int _7200_DO_DMA_Status (U8 *status , U32 *count) @ Argument status : status of the DMA data transfer 0 : DO_DMA_STOP : DMA is completed 1 : DO_DMA_RUN : DMA is not completed count : the numbers of DO data which has been transferred. @ Return Code ERR_NoError 5.26 _7200_DO_DMA_Stop @ Description This function is used to stop the DMA DO operation. After executing this function, the _7200_DO_DMA_Start function is stopped.
5.27 _7200_DI_Timer @ Description This function is used to set the internal timer pacer for digital input. There are two configurations for the internal timer pacer : 1. Non-cascaded (One COUNTER 0 only) 8254 Timer/Counter 4MHz Input Counter 0 CLK0 GATE0 OUT0 Digital Input Trigger Timer pacer frequency = 4Mhz / C0 2.
Note : Since the Integer type in Visual Basic is signed integer. Its range is within -32768 and 32767. In Visual Basic, if you want to set c0 or c2 as value larger than 32767, please set it as the intended value minus 65536. For example, if you want to set c0 as 40000, please set c0 as 40000-65536=-25536. mode : TIMER_NONCASCADE or TIMER_CASCADE @ Return Code ERR_NoError ERR_InvalidBoardNumber ERR_InvalidTimerMode ERR_BoardNoInit 5.
@ Syntax Visual C++ (Windows 95) int W_7200_DO_Timer (U16 c1, U16 c2, Booelan mode) Visual Basic (Windows 95) W_7200_DO_Timer (ByVal c1 As Integer, ByVal c2 As Integer, ByVal mode As Byte) As Long C/C++ (DOS) int _7200_DO_Timer (U16 c1, U16 c2, Boolean mode) @ Argument c1 : frequency divider of Counter #1 c2 : frequency divider of Counter #2 Note : Since the Integer type in Visual Basic is signed integer. Its range is within -32768 and 32767.
6 Double Buffer Mode Principle The data buffer for double-buffered DMA DI operation is a circular buffer logically. It logically divided into two equal halves. The double-buffered DI begins when device starts writing data into the first half of the circular buffer (Figure 6-1a). After device begins writing to the second half of the circular buffer, you can copy the data from the first half into the transfer buffer (Figure 6-1b).
The PCI-7200 double buffer mode functions were designed according to the principle described above. If you use _7200_DblBufferMode() to enable double buffer mode, the following _7200_DI_DMA_Start() will perform double-buffered DMA DI. You can call _7200_CheckHalfReady() to check if data in the circular buffer is half-full and ready for copying to the transfer buffer. Then you can call _7200_DblBufferTransfer() to copy data from the ready half buffer to the transfer buffer.
7 Limitation The 12 MB/sec data transfer rate can only be possibly achieved in a system in which the PCI-7200 card is the only device using the bus, but the speed can not be guaranteed due to the limited FIFO depth. PCI-7200 supports three input clock modes, internal clock, external clock, and handshaking modes. The first two modes cannot guarantee the input data integrity in high-speed data rate because of the limited FIFO depth and the PCI-bus latency variation.
Product Warranty/Service Seller warrants that equipment furnished will be free form defects in material and workmanship for a period of one year from the confirmed date of purchase of the original buyer and that upon written notice of any such defect, Seller will, at its option, repair or replace the defective item under the terms of this warranty, subject to the provisions and specific exclusions listed herein.
