Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
133
8.2.5.1 MPC — Miscellaneous Port Configuration
Table 172. Offset D8h: MPC — Miscellaneous Port Configuration
Size: 32 bit Default: 00110000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
D8h
DBh
Bit Range Default Access Acronym Description
31 0 RW PMCE
Power Management SCI Enable: This enables SCI for power
management events.
30 0 RW HPCE Hot Plug SCI Enable: This enables SCI for hot plug events.
29 0 RW LHO
Link Hold Off: When set, the port will not take any TLP. It is used during
loopback mode to fill the downstream queue.
28 0 RW ATE
Address Translator Enable: This enables address translation via AT
during loopback mode.
27 : 21 0000000 RO RSVD Reserved
20 : 18 100 RW UCEL Unique Clock Exit Latency: L0s Exit Latency when LCAP.CCC is cleared.
17 : 15 010 RW CCEL Common Clock Exit Latency: L0s Exit Latency when LCAP.CCC is set.
14 : 12 000 RW RSVD Reserved
11 : 08 0 RW AT
Address Translator: During loopback, these bits are XORd with bits
[31:28] of the receive address when ATE is set.
07 : 02 000000 RO RSVD Reserved
01 0 RW HPME
Hot Plug SMI Enable: This enables the port to generate SMI for hot
plug events.
00 0 RW PMME
Power Management SMI Enable: This enables the port to generate
SMI for power management events.