Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
134
8.2.5.2 SMSCS — SMI / SCI Status
Table 173. Offset DCh: SMSCS — SMI / SCI Status
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
DCh
DFh
Bit Range Default Access Acronym Description
31 0 RWC PMCS
Power Management SCI Status: This is set if the root port PME control
logic needs to generate an interrupt and this interrupt has been routed to
generate an SCI.
30 0 RWC HPCS
Hot Plug SCI Status: This is set if the hot plug controller needs to
generate an interrupt and this interrupt has been routed to generate an
SCI.
29 : 05 0 RO RSVD Reserved
04 0 RWC HPLAS
Hot Plug Link Active State Changed SMI Status: This is set when
SLSTS.LASC transitions from ‘0’ to ‘1’ and MPC.HPME is set. When set,
SMI_B is generated.
03 : 02 0 RO RSVD Reserved
01 0 RWC HPPDM
Hot Plug Presence Detect SMI Status: This is set when SLSTS.PDC
transitions from ‘0’ to ‘1’ and MPC.HPME is set. When set, SMI_B is
generated.
00 0 RWC PMMS
Power Management SMI Status: This is set when RSTS.PS transitions
from ‘0’ to ‘1’ and MPC.PMME is set. When set, SMI_B is generated.