Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
204
11.1.5.4 Offset 40h, 41h, 42h: Counter Access Ports Register
11.1.6 Timer Programming
The counter/timers are programmed in the following fashion:
1. Write a control word to select a counter
2. Write an initial count for that counter.
Table 301. 40h, 41h, 42h: Interval Timer Status Byte Format Register
Size: 8 bit Default: 0XXXXXXXb Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
40h, 41h, 42h
Bit Range Default Access Acronym Description
07 0 RO CL
Counter State: When set, OUT of the counter is set. When cleared, OUT
of the counter is 0.
06 Undef RO
Count Register: When cleared, indicates when the last count written to
the Count Register (CR) has been loaded into the counting element (CE)
and is available for reading. The time this happens depends on the
counter mode.
05 :04 Undef RO
Read/Write Selection: These reflect the read/write selection made
through bits[5:4] of the control register. The binary codes returned
during the status read match the codes used to program the counter
read/write selection.
00 = Counter Latch Command
01 = Read/Write Least Significant Byte (LSB)
10 = Read/Write Most Significant Byte (MSB)
11 = Read/Write LSB then MSB
03 :01 Undef RO RSVD
Mode: Returns the counter mode programming. The binary code
returned matches the code used to program the counter mode, as listed
under the bit function above.
Table 302. 40h, 41h, 42h: Counter Access Ports Register
Size: 8 bit Default: Undefined Power Well: Core
Access
PCI Configuration B:D:F
Offset Start:
Offset End:
40h, 41h, 42h
Bit Range Default Access Acronym Description
07 :00 Undef RW
Counter Port: Each counter port address is used to program the 16-bit
Count Register. The order of programming, either LSB only, MSB only, or
LSB then MSB, is defined with the Interval Counter Control Register at
port 43h. The counter port is also used to read the current count from the
Count Register, and return the status of the counter programming
following a Read Back Command.
Bits Mode Description
000 0 Out signal on end of count (=0)
001 1 Hardware retriggerable one-shot
x10 2 Rate generator (divide by n counter)
x11 3 Square wave output
100 4 Software triggered strobe
101 5 Hardware triggered strobe