Datasheet

ACPI Devices
Intel
®
Atom™ Processor E6xx Series Datasheet
248
The processor only supports Mode 0.
Commands, Addresses and Data are shifted most significant bit (MSB) first. For the 24-
bit address, this means bit 23 is shifted first while bit 0 is shifted last. However, for data
bursts, bytes are shifted out from least significant byte to most significant byte, where
each byte is shifted (MSB to LSB).
11.9.4.1.1 Addressing
A Slave is targeted for a cycle when it’s SPI_CS# pin is asserted. Besides Slave
addressing there is register addressing within the Slave itself. The list of processor
supported devices’ includes only FLASH devices. See supported devices data sheets for
more information.
11.9.4.1.2 Data Transaction
All transactions on the SPI bus must be a multiple of 8 bits. A frame consists of any
number of 8-bit data packets. To initiate a data transfer, the SPI Master asserts (high to
low transition) the SPI_CS# signal informing the SPI Slave that it is being targeted for a
cycle. The Master will then shift out the 8-bit opcode followed by the Slave’s internal
address.
In the case of a Read transaction, the Slave will interpret the Slave address and begin
driving data out on the SPI_MISO pin and ignore any transactions on the SPI_MOSI pin.
The Master indicates Read complete by deasserting the SPI_CS# signal on an 8-bit
boundary.
In the case of a Write transaction, the Slave will continue to receive Master data on the
SPI_MOSI pin. The Write transaction is completed upon deassertion of the SPI_CS#
signal on an 8-bit boundary
The SPI bus does include a mechanism for flow control, however some devices include
the support of a HOLD signal. See Slave documentation for more information. If the
Slave receives an un-recognized or invalid opcode it should ignore the rest of the packet
and wait for the deassertion of SPI_CS#.
11.9.4.1.3 Bus Errors
If the first 8 bits specify an opcode which is not supported the slave will not respond and
wait for the next high to low transition on SPI_CS#.
SPI hardware should automatically discard 8-bit words that were not completely
received upon deassertion of the SPI_CS# signal.
Any other error correction or detection mechanisms must be implemented in
firmware/software.
11.9.4.1.4 Instructions
Table 370. Instructions (Sheet 1 of 2)
Instruction ST* M25P80
(8 Mb)
ST* M45P80
(8 Mb)
NexFlash* NX25P SST* 25V040 (4 Mb)
SST* 25VF080 (8 Mb)
Write Status 01 - 01 01
Data Program 02 02 02 02
Read Data 03 03 03 03
Write Disable 04 04 04 04
Read Status 05 05 05 05