Datasheet

Signal Description
Intel
®
Atom™ Processor E6xx Series Datasheet
37
2.8 Power Management Interface Signals
Table 12. Power Management Interface Signals
Signal Name
Direction/
Type
Power
Well
Description
RESET_B
I
CMOS3.3
SUS
System Reset: Active Low Hard Reset for the processor.
When asserted, the processor will immediately initialize itself
and return to its default state. This signal is driven by the
Power Management IC.
PWROK
I
CMOS3.3
RTC
Power OK: When asserted, PWROK is an indication to the
system that core power is stable. PWROK can be driven
asynchronously.
RSMRST_B
I
CMOS3.3
RTC
Resume Well Reset: This signal is used for resetting the
resume well. An external RC circuit is required to ensure that
the resume well power is valid prior to RSMRST_B going high.
RTCRST_B
I
CMOS3.3
RTC
RTC Well Reset: This signal is normally held high, but can
be driven low on the motherboard to test the RTC power well
and reset some bits in the RTC well registers that are
otherwise not reset by SLPMODE or RSMRST_B. An external
RC circuit on the RTCRST_B signal creates a time delay such
that RTCRST_B will go high some time after the battery
voltage is valid. This allows the chip to detect when a new
battery has been installed. The RTCRST_B input must always
be high when other non-RTC power planes are on.
SUSCLK
O
CMOS3.3
SUS
Suspend Clock: This signal is an output of the RTC
generator circuit (32.768 kHz). SUSCLK can have a duty
cycle from 30% to 70%.
WAKE_B
I
CMOS3.3
SUS
PCI Express* Wake Event: This signal indicates a PCI
Express* port wants to wake the system.
This is a single signal that can be driven by any of the devices
sitting on the PCIe* slots on the board. It is normally pulled
high (by the devices), but any devices that need to wake the
processor will drive this signal low.
SLPMODE
O
CMOS3.3
SUS
Sleep Mode: SLPMODE determines which sleep state is
entered. When SLPMODE is high, S3 will be chosen. When
SLPMODE is low, S4/S5 will be the selected sleep mode.
RSTWARN
I
CMOS3.3
SUS
Reset Warning: Asserting the RSTWARN signal tells the chip
to enter a sleep state or begin to power down. A system
management controller might do so after an external event,
such as pressing of the power button or occurrence of a
thermal event.
SLPRDY_B
O
CMOS3.3
SUS
Sleep Ready: The processor will drive the SLPRDY_B signal
low to indicate to the system management controller that the
processor is awake and able to placed into a sleep state.
Deassertion of this signal indicates that a wake is being
requested from a system device.
RSTRDY_B
O
CMOS3.3
SUS
Reset Ready: Assertion of the RSTRDY_B signal indicates to
the system management controller that it is ready to be
placed into a low power state. During a transition from S0 to
S3/4/5 sleep states, the chip asserts RSTRDY_B and
CPURST_B after detecting assertion of the RSTWARN signal
from the external system management controller
GPE_B
I
CMOS3.3_OD
SUS
General Purpose Event: GPE_B is asserted by an external
device (typically, the system management controller) to log
an event in the chip’s ACPI space and cause an SCI (if
enabled).