Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
79
four 8-bit values. When considered as four 8-bit values, the integer unit effectively acts
like a four-way SIMD ALU, performing four operations per clock. It is expected that in
legacy applications pixel processing will be done on 8-bit integers, roughly quadrupling
the pixel throughput compared to processing on float formats.
7.2.6 Multi Level Cache
The multi-level cache is a three-level cache system consisting of two modules, the main
cache module and a request management and formatting module. The request
management module also provides Level-0 caching for texture and unified shader core
requests.
The request management module can accept requests from the data scheduler, unified
shaders and texture modules. Arbitration is performed between the three data
streams, and the cache module also performs any texture decompression that may be
required.
7.3 Video Encode
The Intel
®
Atom™ Processor E6xx Series supports full hardware video encode. The
video encode hardware accelerator improves video capture performance by providing
dedicated hardware-based acceleration. Other benefits are low power consumption, low
host processor load, and high picture quality. The processor supports full hardware
acceleration of the following video encode:
• Permits 720P30 H.264 BP encode
• MPEG4 encode and H.263 video conferencing
With integrated hardware encoding the host processor only needs to deal with higher-
level control code functions, such as providing the image to encode and processing the
video elementary stream.
The processor supports a standard definition video encoder that has as an input, a
series of frames which are encoded to produce an elementary bit stream. This section
describes the top level interactions between all modules contained in encode hardware.
7.3.1 Supported Input Formats
The following input formats are supported for the video input planar Luma and planar
or interleaved Chroma 4:2:0. The following is a list of the formats:
• YUV IMC2 Planar Pixel Format
• YUV YV12 Planar Pixel Format
• YUV PL8 Planar Pixel Format
• YUV PL12 Planar Pixel Format
The first stage is to fetch the data in its original format UYVYUYVYUYVYUYVY and then
translate this to the following format UVUVUVUV YYYYYYYY. Only the Chroma data is
TDMA’d back to the EIOB and then TDMA’d from the EIOB back into the ESB again to
de-interleave the chroma components.
7.3.1.1 Encoding Pipeline
In general, the encoding process is pipelined into a number of stages. For MPEG-
4/H.263/H.264 encoding, the data is processed in macroblocks, with a minimum of
interaction from the embedded controller within each processing stage.