Datasheet

Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
87
7.5.2.1 LVDS Port
A single LVDS channel only is supported. The single LVDS channel can support clock
frequency ranges up to a maximum pixel clock rate up to 80 MHz.
The graphics core is responsible to read the EDID ROM from the installed panel (if
present) specifications through I
2
C* interface and the software driver uses it to
program the pipe A timing registers.
The Intel
®
Atom™ Processor E6xx Series supports a single LVDS channel with several
modes and data formats. The single LVDS channel consists of 4 data pairs and a clock
pair. The phase locked transmit clock is transmitted over the LVDS clock pair in parallel
with the data being sent out over the data pairs. The pixel serializer supports 8-bit or
6-bit per color channel. The display data from the display pipe is sent to the LVDS
Figure 7. Display Resolutions