PLMP Report

Test Notes
Windows 7
Windows 7 64-bit
PCI Hardware
Compliance
Test For
Systems
12/1/2010
1241
Erratum
This happens because the PCI Compliance test assumes that if the
Data Link Layer Link Active Reporting Capable bit in the Link
Capabilities register for a given PCIe port is set then that indicates
that the Data Link Layer Link Active bit will also be set. This is an
incorrect assumption because the Data Link Link Layer Link Active bit
can be reset when there is no device below the port. This assertion
needs to be removed from the PCIHCT. The current architecture of
the PCIHCT prevents it from knowing whether devices exist below a
bridge/port.
Windows 7
Windows 7 64-bit
PCI Hardware
Compliance
Test For
Systems
12/1/2010
401
Erratum
The following PCI Compliance test failure is acceptable: Bit 15 (Bridge
Configuration Retry Enable) in the Device Control register (offset 8h)
in the PCI Express Capability table must be read-only and always
return 0 as it is reserved for devices other than PCI Express to
PCI/PCI-X Bridges. Assertion 13A41D3E-2576-41DC-A67C-
525DA3637CEA This failure is acceptable because this is a PCIe 1.1
feature and the WLP requires compliance with only PCIe 1.0a.
Operating System
Test
Description
Windows 7
BIOS
download
Internal: http://bios.intel.com/downloads/
External: http://www.intel.com/ click on Support and Download
Windows 7
BIOS setup
Please make sure the BIOS setting are as below, otherwise use default
settings.
System Date and Time: Current date and time
Peripheral Configuration: Enable all onboard component
Drive Configuration: Set to IDE
Chipset Configuration: Enable HPET
ACPI Suspend State: Set to <S3 State>
Boot Device Priority: set <Hard Disk Driver> to first
Windows 7 filter
update
WLK WHQL
test
http://winqual.microsoft.com/member/SubmissionWizard/LegalExemptions/filte
rupdates.cab
Special H/W that
use to PASS the
test
None
None