MLP Report

Errata and Contingencies
Operating System Failing Test
Expiry
date ID Number Type Error Description
Windows Vista
Windows Vista 64-bit
PCI Hardware
Compliance
Test For
Systems
Running
Windows Vista
(PCIHCT)
3/5/2008 990
Erratum
The Bit 5 (Surprise Down Error Severity) in the
Uncorrectable Error Severity register (offset Ch) in the
Advanced Error Reporting Capability table must be read-only
and always return 1 if the Bit 5 (Surprise Down Error Mask)
in the Uncorrectable Error Mask Register in the Advanced
Errror Reporting Capability table is not implemented
Windows Vista
Windows Vista 64-bit
PCI Hardware
Compliance
Test For
Systems
Running
Windows Vista
(PCIHCT)
12/31/20
08
385
Erratum
The following PCI Compliance test failure is acceptable: Bit
15 (Bridge Configuration Retry Enable) in the Device Control
register (offset 8h) in the PCI Express Capability table must
be read-only and always return 0 as it is reserved for
devices other than PCI Express to PCI/PCI-X Bridges.
Assertion 13A41D3E-2576-41DC-A67C-525DA3637CEA
This failure is acceptable because this is a PCIe 1.1 feature
and the WLP requires compliance with only PCIe 1.0a.
Windows Vista
Windows Vista 64-bit
PCI Hardware
Compliance
Test For
Systems
Running
Windows Vista
(PCIHCT)
12/31/20
08
709
Erratum
Certain devices are known to have incompatibilities with the
test causing a system hang during testing. This erratum is
for those devices The PCIHCT tests Bit 15 of the Device
Control Register in the PCI Express Capability table. The
testing of Bit 15, specifically the writing of a 1 to the bit
causes a function level reset making the device unavailable
for a maximum of 100ms. All writes to the PCI config space
of the device are ignored during the reset. All reads to the
PCI config space of the device return all ones (1). This
confuses the PCIHCT test and it incorrectly fails the
assertions for Bits 4, 11, 12, 13 and 14. Assertion
73C19B53-84B8-4BA4-97EA-3FF6DEF57273: FAILED. Bit 4
(Enable Relaxed Ordering) in the Device Control register
(offset 8h) in the PCI Express Capability table must be read-
writable if it's implemented. Assertion C0846E74-2CFE-
4CC2-A492-6AAF16F206CD: FAILED. Bit 11
(Enable No
Snoop) in the Device Control register (offset 8h) in the PCI
Express Capability table must be read-writable if it's
implemented. Assertion A56B0EE0-0C2C-47A4-90C4-
5F8EEB30D427: FAILED. Bit range 14:12
(Max_Read_Request_Size)in the Device Control register
(offset 8h) in the PCI Express Capability table must be read-
writable if implemented. Assertion 13A41D3E-2576-41DC-
A67C-525DA3637CEA: FAILED. Bit 15 (Bridge Configuration
Retry Enable) in the Device Control register (offset 8h) in
the PCI Express Capability table must be read-only and
always return 0 as it is reserved for devices other than PCI
Express to PCI/PCI-X Bridges.
Windows Vista
Windows Vista 64-bit
Windows XP Pro
UAA Test -
Vista (System)
7/31/200
8
534
Erratum
UAA Test requires the Traffic Priority bit to be read/write -
however there are two specs that apply, and they conflict.
One says the bit must be read/write, the other says it must
be read-only. Contact has been made with the author of
both specs (Intel) but until this point is clarified we cannot
fail submissions containing this test failure.