MLP Report

Window 7
Class Driver
Fidelity Test -
Win7 (System,
Manual)
12/01/2009 1670
Erratum
EU restrictions place a cap on the output level of headphone
jacks at 32 Ohm load: headphones are not allowed to have an
electrical output of more than 150 mV at that load.
We test headphone jacks at 300 Ohm load; the relationship
between the output at 32 Ohms and the output at 320 Ohms
depends on the output impedance of the headphone jack.
In particular, if a headphone jack meets the EU requirement of
X <= 150 mV at 32 Ohms, depending on the output impedance,
it could output a huge amount of power at 300 Ohms, or very
slightly over X mV. Since we require X >= 120 mV at 32 Ohms,
absent knowledge of the output impedance we can only
require X >= 120 mV at 300 Ohms.
120 mV is -18.42 dBV. Any headphone output level at 32
Ohms that is less than -18.42 dBV is a legitimate failure, even
if it is targeted at EU compliance. Any headphone output level
greater than 1 Vrms (0.707 Vrms for mobile systems) is a
legitimate pass, regardless of EU compliance.
This errata covers output level failures for headphone jacks
between -18.42 dBV and 1 Vrms/0 dBV (0.707 Vrms/-6.93
dBV for mobile systems)) in accordance with note 6 of the WLP
fidelity requirements.
Windows 7
PCI Hardware
Compliance
Test For
Systems
12/31/2009 1029
Erratum
Assertion B576282C-5C66-4253-A275-257F5D49EFEF
SSVID register of the Subsystem ID and Subsystem Vendor ID
Capability table cannot have a value of 0h .
Assertion 4BA8F23A-6BB1-48EE-88D8-ED1A3ECD34B9
SSVID register of the Subsystem ID and Subsystem Vendor ID
Capability table must be read-only .
Assertion 6B0F606E-DBB3-4B8C-8879-32B302412EB8
SSID register of the Subsystem ID and Subsystem Vendor ID
Capability table must be read-only .
Assertion 7A5587BC-5646-4DC4-9A5D-22F85AB2204E
PCI Express ports and bridges must implement Subsystem ID
and Subsystem Vendor ID Capability.
Windows 7
PCI Hardware
Compliance
Test For
Systems
06/01/2010 1543
Erratum
This happens because the PCI Compliance test assumes that if
the Data Link Layer Link Active Reporting Capable bit in the
Link Capabilities register for a given PCIe port is set then that
indicates that the Data Link Layer Link Active bit will also be
set. This is an incorrect assumption because the Data Link Link
Layer Link Active bit can be reset when there is no device
below the port. This assertion needs to be removed from the
PCIHCT. The current architecture of the PCIHCT prevents it
from knowing whether devices exist below a bridge/port.
Windows 7
UAA Test -
Win7 (System)
12/01/2009 1394
Erratum
UAA Test requires the Traffic Priority bit to be read/write -
however there are two specs that apply, and they conflict. One
says the bit must be read/write, the other says it must be
read-only. Contact has been made with the author of both
specs (Intel) but until this point is clarified we cannot fail
submissions containing this test failure.