MLP Report

Errata and Contingencies
Operating System
Failing Test
Expiry Date
ID Number
Type
Error Description
Windows Vista
Windows Vista 64bit
Windows 7
Windows 7 64
-bit
PCI Hardware
Compliance Test For
Systems
12/01/2012
401
Erratum
The foll
owing PCI Compliance test failure is acceptable: Bit 15
(Bridge Configuration Retry Enable) in the Device Control register
(offset 8h) in the PCI Express Capability table must be read
-only
and always return 0 as it is reserved for devices other than PCI
Ex
press to PCI/PCI-X Bridges. Assertion 13A41D3E-2576-41DC-
A67C
-525DA3637CEA This failure is acceptable because this is a
PCIe 1.1 feature and the WLP requires compliance with only PCIe
1.0a.
Windows Vista
Windows Vista 64bit
Windows 7
Windows 7 64
-bit
PC
I Hardware
Compliance Test For
Systems
12/01/2012
1241
Erratum
This happens because the PCI Compliance test assumes that if the
Data Link Layer Link Active Reporting Capable bit in the Link
Capabilities register for a given PCIe port is set then that indic
ates
that the Data Link Layer Link Active bit will also be set. This is an
incorrect assumption because the Data Link Link Layer Link Active
bit can be reset when there is no device below the port. This
assertion needs to be removed from the PCIHCT. The cu
rrent
architecture of the PCIHCT prevents it from knowing whether
devices exist below a bridge/port.
Windows Vista
Windows Vista 64bit
Windows 7
Windows 7 64
-bit
1)
UAA Test - Vista
or Server08
(System)
2)
UAA Test - Win7
(System)
6/1/201
5
513
Erratum
UAA Test requires the Traffic Priority bit to be read/write -
however there are two specs that apply, and they conflict. One
says the bit must be read/write, the other says it must be read
-
only. Contact has been made with the author of both specs (Intel)
but until this point is clarified we cannot fail submissions containing
this test failure.