PLMP Report

Errata and Contingencies
Operating System
Failing Test
Expiry
Date
ID
Number
Type
Error Description
Windows 7
Windows 7 64-bit
Class Driver AC3
Test - Win7
(System)
6/30/2025
1256
Erratum
Run AC3 test on a system with the Microsoft HD Audio class
driver installed. Expected results: All AC3 kernel streaming data
ranges should advertise MinimumBitsPerSample = 16 and
MaximumBitsPerSample = 16. Actual results: HD Audio class
driver sometimes advertises MaximumBitsPerSample = 24.
Windows 7
Windows 7 64-bit
PCI Hardware
Compliance Test
For Systems
12/31/2011
2051
Erratum
PCIHCT - Bit range 11:10 (ASPM Support)in the Link Capabilities
register (offset Ch) in the PCI Express Capability table is 0h. It
cannot be in the set of values {0x0, 0x2}. (Assertion 5CAF4993-
B8D1-4E4E-99EC-CC5895364E32)
Windows 7
Windows 7 64-bit
PCI Hardware
Compliance Test
For Systems
6/1/2011
423
Erratum
Assertion 5CAF4993-B8D1-4E4E-99EC-CC5895364E32 Bit
range 11:10 (ASPM Support)in the Link Capabilities register
(offset Ch) in the PCI Express Capability table is 0h. It cannot be
in the set of values {0x0, 0x2}.
Windows 7
Windows 7 64-bit
PCI Hardware
Compliance Test
For Systems
6/1/2011
401
Erratum
The following PCI Compliance test failure is acceptable: Bit 15
(Bridge Configuration Retry Enable) in the Device Control
register (offset 8h) in the PCI Express Capability table must be
read-only and always return 0 as it is reserved for devices other
than PCI Express to PCI/PCI-X Bridges. Assertion 13A41D3E-
2576-41DC-A67C-525DA3637CEA This failure is acceptable
because this is a PCIe 1.1 feature and the WLP requires
compliance with only PCIe 1.0a.
Windows 7
Windows 7 64-bit
PCI Hardware
Compliance Test
For Systems
6/1/2011
923
Erratum
Assertion FAE18121-9177-4FB2-A081-0D04C285EFF2 Bit
range 15:0 (Extended Capability ID)in the Enhanced Capability
Header register (offset 0h) in the Unrecognized Enhanced
Capability ID 13 table is Dh. It must be in the range [0x0 - 0xB]
as all other Capability IDs are reserved.
Windows 7
Windows 7 64-bit
PCI Hardware
Compliance Test
For Systems
12/1/2012
1241
Erratum
This happens because the PCI Compliance test assumes that if
the Data Link Layer Link Active Reporting Capable bit in the Link
Capabilities register for a given PCIe port is set then that
indicates that the Data Link Layer Link Active bit will also be set.
This is an incorrect assumption because the Data Link Link
Layer Link Active bit can be reset when there is no device
below the port. This assertion needs to be removed from the
PCIHCT. The current architecture of the PCIHCT prevents it from
knowing whether devices exist below a bridge/port.