Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
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The number of isochronous streams which can be simultaneously serviced is a function of the core
logic implementation and therefore not specified here. Designers must refer to the targeted core logic
documentation for any implementation specific restrictions that must be observed.
4.1.3 Transaction Ordering
There is no ordering between the completion of isochronous memory transactions and the completion
of any other memory traffic in the system. Further, there is no ordering between completions of
isochronous read and write transactions.
4.1.3.1 Read Completion Order
AGP3.0 core-logics return isochronous read data in the same order as the corresponding isochronous
read requests. The underlying memory read operations might be performed in an order different from
the isochronous read request order.
An AGP3.0 memory read transaction is complete when all of the data have been returned to the device
from system memory.
4.1.3.2 Write Completion Order
AGP3.0 core-logics transfer isochronous write data across the AGP3.0 Port in the same order as the
isochronous write requests; however, this does not constitute completion of the write transaction. An
AGP3.0 “memory write” transaction is complete when the data is globally visible. There are two
isochronous write transaction types that differ in their completion order.
Unfenced isochronous write transactions
Unfenced isochronous write transactions may complete in a different order from the corresponding
unfenced write requests and cannot be relied upon for producer/consumer synchronization.
Consider two unfenced isochronous write operations to the same target memory address:
Unfenced Isochronous Write A, Unfenced Isochronous Write B. B is not required to overwrite A
Chipsets that reorder unfenced write transactions memory completions may be able to sustain higher
overall memory performance. AGP3.0 core-logics that do not reorder unfenced isochronous write
operations are allowed to substitute fenced writes instead.
Fenced isochronous write transactions
Fenced isochronous write transactions complete in memory after all previously requested write
isochronous transactions (of either kind) are completed.
Consider two isochronous write operations to the same target memory address, the second transaction
being a fenced isochronous write:
Isochronous Write A, Fenced Isochronous Write B. B will overwrite A
Fenced write transactions provide a convenient means for synchronizing an AGP3.0 device with the
host processor using the producer/consumer model. The AGP3.0 Master device may write a block of