Accelerated Graphics Port Interface Specification
AGP3.0 Interface Specification
Rev. 1.0
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4.1.7 Identifying Isochronous Data
The AGP3.0 core-logic specifies the type of isochronous data to be transmitted over the AGP3.0 Port
using the two status codes that were previously reserved. The new status codes are shown below.
Highlighting implies a change from AGP2.0.
Table 51: Isochronous Status ID Codes
Status Data Type
000 Asynchronous read or flush return
001 Reserved
010 Asynchronous write data
011 Reserved
100 Isochronous memory read data
101 Isochronous memory write data
110 Calibration Cycle
111 Master has been given permission to start a bus transaction
4.1.8 Flow Control
The AGP3.0 Master device may delay the transmission of returning isochronous write data up to one
common clock by delaying the assertion of IRDY# for one clock. The AGP3.0 core-logic may delay the
start of a read data transfer by up to one common clock by delaying the assertion of TRDY# by one
clock
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. The Core Logic should ensure that Calibration Cycles will not violate Isochronous latency.
Once an isochronous data transfer begins it goes to completion without interruption.
Asynchronous transactions allow flow control for every four common clocks during data transmission,
whereas, isochronous data transmission is never interrupted. The longest duration isochronous data
payload (8X signaling speed and 256 byte data transfers) takes eight clocks. No flow control is allowed
during the entire data transmission phase. The non-isochronous flow control signals RBF and WBF
have no effect on isochronous transactions. When the isoch device asserts these signals, the core-
logic may choose to ignore them.
4.1.9 Isochronous Bridges
AGP3.0 systems may contain an optional Fan-out Bridge component for connecting two AGP3.0 Master
devices to the system. Each AGP3.0 device may read or write main system memory using
isochronous transactions as specified above. The processor may use PCI transactions to write data to
either AGP3.0 device in the usual way. If two AGP3.0 devices must communicate, they must do it
through a section of system memory to which they both have access.
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The same is true for AGP.