Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
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uses the GART for translation.
10. The operation of the AGP Port and AGP Master accesses to system memory function correctly
regardless of whether host translation is present in the core-logic.
11. It is implementation-dependent whether the core-logic translates accesses directed to the AGP
aperture by any system component NOT on the AGP Port – including PCI devices on other Buses.
Software should not rely on this capability.
12. Core-logic indicates which AGP aperture page sizes are supported through the NEPG register.
System software selects one page size from the set of supported AGP aperture page sizes by
programming the value into the NEPG.SEL.
13. A core-logic implementation must always support an AGP aperture page size of 4KB;
implementations are encouraged, but not required to support other AGP aperture page sizes. (Note
that NEPG defaults to selecting 4KB AGP aperture pages).
14. Software must use the procedure described in Section 5.3.5 to relocate and resize the AGP
aperture during normal system operation.
5.3.3 GART Overview
The GART is a re-mapping table of translations for accesses to the AGP aperture. The GART resides
in system RAM. Each aligned AGP aperture page has a corresponding GART entry, which translates it.
AGP allows the GART to be organized in a DIRECT-MAPPED format; an offset into the AGP aperture is
scaled down and used as an index to point directly to a GART entry in the GART.
A GART entry is marked as a valid translation when its corresponding valid bit is set. System software
ensures that all GART entries needed to translate AGP aperture addresses are valid. If, when
attempting to translate an AGP aperture address, core-logic accesses an invalid GART entry, it
performs a platform specific exception action.
AGPCTRL.gtlben controls the caching of GART entries in an implementation-defined GTLB.
5.3.4 GART Requirements
1. The GART resides in the system physical address space and is pointed to by the address in the
GARTLO and GARTHI configuration registers. It can be directly accessed by host software using
memory or memory-mapped I/O addressing. For sake of discussion:
GART_START = (GARTHI << 32) + ( GARTLO & 0xFFFFF000)
2. The starting location of the GART is always 4KB-aligned.
3. When the AGP aperture is enabled. The GART is always enabled; there is no way to turn off the
GART without disabling the AGP aperture.
4. The core-logic implementation chooses one width for all GART entries; the width is either 32 or 64-
bits. The supported widths are reported by AGPSTAT.gart64b; software should program
AGPCMD.gart64b to pick the width for operation. See Section 5.8.5 for details.The format of a GART
entry is shown below. (This format in conjunction with larger AGP aperture page sizes, allows an
implementation to keep using 32-bit GART entries even as physical addresses grow larger than 40-
bits. The format is also compatible with the i440BX style GART entries)
Let, SPFN[63:0] = Zero_Extend( Target_Physical_Address) >> log2( Aperture_Page_Size)