Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
119
Table 55: Bit Positions
Bit Position Field Definition
0 Valid When 1, the GART entry is a valid translation. When 0, the GART entry
is invalid and accessing the entry for translation causes an
implementation specific error condition..
1 Coh This bit in combination with AGPSTAT.ITA_COH controls coherency
support for accesses that use this GART entry. See section 5.4 for
details.
3:2 Rsv
Reserved for future use by the AGP3.0 specification. SBZ
1
.
11:4 SPFN1 SPFN[27:20]. In a 4KB-GART-page implementation, with 32-bit
Physical Addressing, these bits will be ‘0’
31:12 SPFN0 SPFN[19:0]. In a 4KB-GART-page implementation, with 32-bit Physical
Addressing, these bits will correspond to the bits[31:12] of the target
Physical Address.
All bits are valid and must be filled in by software.
63:32 SPFN2 SPFN[59:28]. Only present in a 64-bit width GART entry.
/ NOTE
1
Software should write zero to these bits; AGP3.0 requires that a value of zero will always
produce backward compatible behavior in all future implementations that define these bits.
The GART must reside in a physically contiguous memory. The size of the entire GART is:
GART_Size = (Aperture_Size / Aperture_Page_Size) * 2 ^ (2 + AGPSTAT.gart64b)
5. Each GART entry maps an aligned AGP aperture Page address to an actual physical RAM location.
6. Let M be the log2 number of bytes in a GART entry (either 2 for 4-byte entries or 3 for 8-byte
entries). For an AGP aperture address, A, the corresponding GART entry address is then:
entry_address = GART_START + ( ( (A-Aperture_Base) >> log2(Aperture_Page_Size) ) << M
)
7. Software may locate the GART anywhere within physical RAM addresses; the GART cannot be
located in Memory-Mapped I/O space. The core-logic cannot place constraints on where the GART
can be located within physical RAM addresses.
8. Core-logic accesses to the GART are not guaranteed to be coherent with host processor caches. In
order to avoid having to flush the cache after every GART update, portable system software should
place the GART in a range of the physical memory space that is considered un-cacheable by host
processors. (A good example is mapping the GART as UC in an Intel Pentium II processor).
However, the specification does not preclude the placement of the GART in cachable memory
space in cases where the coherency is guaranteed through some hardware or software
mechanism.
9. Attempting to translate an AGP aperture address through an invalid GART entry is a non-recoverable
error condition. When this happens, core-logic does the following: