Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
120
a) It sets an implementation specific error bit and optionally records the invalid GART entry address
in an implementation specific register. These remain latched until explicitly cleared by software
or on Power-On-Reset.
b) Core-logic causes a processor-specific action that is platform dependent.
c) If the transaction is a read of the AGP aperture, core-logic may either cancel the request or
complete the request by returning UNDEFINED data.
d) If the transaction is a write of the AGP aperture, core-logic cancels the request.
10. Core-logic supports modification of the GART during normal system operation provided that
software follows the procedure outlined in Section 5.3.5.
11. The caching of GART entries in an implementation defined GTLB is controlled by AGPCTRL.gtlben.
12. Core-logic must support the aliasing (or mapping) of multiple AGP aperture pages to the same post-
translated page. The corresponding gart_entry.coh bit, if supported, must apply coherency
attributes.
5.3.5 Requirements for Modifying GART Entries
The following steps assume that the core-logic implements a GART Translation Look-aside Buffer
(GTLB). A GTLB is not a required feature.
1. System software must ensure that all host processor and AGP Master transactions to the AGP Port
and the AGP aperture that could potentially use the candidate GART entries are suspended. Once
suspended, system software must ensure that all previous transactions have been flushed from all
processor write queues that target AGP aperture locations mapped by the candidate GART entries.
2. System software writes ‘0’ to AGPCTRL.gtlben using a strongly ordered, un-cacheable write.
3. System software is now free to modify GART entries using strongly ordered un-cacheable writes.
4. Using mechanisms specific to the operating-system and host processor architecture, system
software needs to update any host processor translations that map the AGP Port or AGP aperture
which are affected by changes to the GART entries.
5. When all modifications are finished, system software issues a strongly ordered, un-cacheable read
for the last datum written to system memory; this ensures that all memory changes have
propagated.
6. System software writes ‘1’ to AGPCTRL.gtlben using a strongly ordered, un-cacheable write.
7. Using mechanisms specific to the operating system and host processor architecture, system
software resumes AGP Port and AGP aperture transactions on all host processors.