Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification

Rev. 1.0

129

Bits Access Field Description

6 MST: RZ-IW

TGT: R-IW-Dx

htrans# TARGET ONLY: When ‘0’, Core-logic can translate host processor

accesses through the AGP aperture. NOTE: Core-logic translation of

host processor accesses is a platform specific feature and is

solely used for the purpose of supporting legacy OS. Drivers

written to use this feature may not port to platforms that do not

have legacy support requirements.

5 R-IW OVER4G

If set, this device supports addresses greater than 4 GB.

4 R-IW FW MASTER & TARGET: If set to a 1, this Master or Target supports

Fast Writes. Fast-Write support is optional for both Master and

Target.

3 R-IW AGP3.0_MODE ‘1’ = AGP3.0 Mode and ‘0’ = AGP Mode; Set by hardware on power-up

reset, see section 2.4.2 for details. Note that when

AGP3.0_MODE = 0, the RATE field (AGPSTAT [2:0]) and DRATE

field (AGPCMD[2:0]) in both the master and target must function

as defined by the AGP Interface Specification V2.0 for compatibility

with existing software.

2:0 R-IW RATE Data Rate Support (RATE) -

AGPSTAT[3] Code Speed Supported

0 xxx See AGP2.0 Specs

1 001 4x

1 010 8x

1 011 4x, and 8x

1 All other codes Reserved

If Target (Core-Logic) sets OVER4G it must support >32bit address PCI cycles generated by the Master using DAC. See

PCI Local Bus Specification V2.2 for details. However, support of outbound DAC transactions from the core-logic to the

graphics card is optional.