Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
130
5.8.5 AGPCMD: AGP COMMAND REGISTER
Offset: CAPPTR + 08h
Size: 4 bytes
Table 65: Command Register
Bits Access Field Description
31:24 MST: R-W-D’0
TGT: RZ-IW
PRQ Master: The PRQ field must be programmed with the
maximum number of AGP command requests (both
asynchronous and isochronous) that the master is
allowed to “enqueue” in the target. “0” means a depth of
one entry, while FFh means a depth of 256 entries.
For a given AGP Port, the sum of all Masters’ adjusted
AGPCMD.PRQ must be less than or equal to the target’s
adjusted AGPSTAT.RQ:
(TARGET.RQ +1) >=(MASTER[i].PRQ + 1) +
(MASTER[i+1].PRQ + 1) + ...
Target: IGNORED.
23:17 RZ-MW Reserved Always returns 0 when read; write operations have no
effect.
16 RZ-MW Reserved Always returns 0 when read; write operations have no
effect. Future use reserved.
15:13
MST: R-W-D’0
TGT: RZ-IW-
D’0
PARQSZ
MASTER ONLY: Programmed based on ARQSZ in
TARGET’s AGPSTAT[15:13]. LOG2 of the optimum
asynchronous request size in bytes minus 4 to be used
with the target. The MASTER should attempt to issue a
group of sequential back-to-back asynchronous requests
that total to this size and for which the group is naturally
aligned to.
Optimum_request_size = 2 ^ (PARQSZ+4)
If ARQSZ is zero, then the target has no recommendation.
12:10
MST: RZ-IW
TGT: R-W-
D’000
PCAL_Cycle
TARGET ONLY: Programmed with period for core-logic
initiated bus cycle for calibrating I/O buffers for both
master and target. The default value is based on chipset
requirements. This value is updated with the smaller of
the value in CAL_CYCLE from Master’s/TARGET’s
AGPSTAT. The translations of the encoding remain the
same as in CAL_CYCLE.
PCAL_CYCLE is set to 111 by s/w when both Master and
Target have AGPSTAT.CAL_CYCLE = 111.
9 R-W-D’0 SBA_ENABLE This must be a read/write bit for software compatibility
with AGP interface specification V2.0. AGP3.0 devices are
required to support side band addressing, so this must
be set to 1 ‘b by the software when AGPSTAT[3] = 1.
8 R-W-D’0 AGP_ENABLE Master: Setting the AGP_ENABLE bit allows the master to