Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
131
Bits Access Field Description
initiate AGP operations. When cleared, the master cannot
initiate AGP operations.
Target: Setting the AGP_ENABLE bit allows the target to
accept AGP operations. When cleared, the target ignores
incoming AGP operations. Notes:
1. The target must be completely configured and
enabled before the master is programmed.
2. A device can make no assumptions as to the
sequence of command field programming, except
that AGP_ENABLE is the last bit set. Concurrently
setting all command fields and the AGP_ENABLE bit
using a single 32-bit write is also permitted.
3. This bit must not be cleared in the target until it has
been cleared in the master. There should be no
outstanding SBA requests in the target when the bit is
cleared.
The AGP_ENABLE bit is cleared by power-on-reset.
7 MST: RZ-IW
TGT: R-W-D’0
GART64B TARGET ONLY: Value is dependent by what is
programmed in AGPSTAT.gart64b as follows:
• If AGPSTAT.Gart64b is a 0 then
AGPCMD.Gart64b will be forced to 0 and is
Read-Only.
• If AGPSTAT.Gart64b=1, the AGPCMD.Gart64b is
R/W and software can set it to 1 for 64 bit entries
or leave it at its default value of 0 for 32 bit
entries.
6 RZ-MW Reserved Always returns 0 when read; write operations have no
effect.
5 R-W-D’0 OVER4G Master: Setting the OVER4G bit allows the master to
initiate AGP3.0 Requests to addresses above the 4 GB
address boundary. When cleared, the master is only
allowed to access addresses in the low 4 GB of the
address space.
Target: Setting the OVER4G bit enables the target to
accept a Type 4 command and to utilize A[35::32] for a
Type 3 command.
4 R-W-D’0 FW_ENABLE MASTER & TARGET: When set to 1, FW is enabled in
Master or Target.
3 RZ-MW Reserved
Always returns ‘0’ on reads. Writes are ignored.