Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification

Rev. 1.0

137

5.9 Required Target Registers

5.9.1 APBASELO: AGP APERTURE BASE LOW ADDRESS REGISTER

Offset:

10h

Size: 4 bytes

Table 68: Aperture Base Low Address Register

Bits Access Field Description

31:22 R-W-D’0 AddressLo Address[31:22] of the AGP3.0 Aperture Address.

Writes to APBASELOW will be dictated by the

programmed value in Apsize. APSIZE[11:8] controls

APBASELOW[31:28] while APSIZE[5:0] controls

APBASELOW[27:22]. Each bit in APBASELOW[31:22]

will be R/W only when the corresponding bit in APSIZE is

set to 1. Otherwise that bit in APBASE will be READ-

ONLY and its value will be forced to 0. See section 5.9.4.

Note that some older implementations may not actually

force APBASELOW register bits to 0 when corresponding

APSIZE bits are a 0. However, the actual internally used

AGP Aperture Base address will have these bits set to 0.

To ensure portable software, the recommended

programming sequence is as follows:

1) Set the bits in APSIZE to 1 to make R/W.

2) Clear APBASELOW

3) Program APSIZE

4) Program APBASELOW

21:4 RZ-IW Zero Bits are hardwired to zero. This forces minimum AGP3.0

aperture size to be 4MB or greater.

3 R1-IW Prefetchable Hardwired to ‘1’ to identify the Graphics AGP3.0 aperture

range as prefetchable -- i.e. there are no side effects on

reads, the device returns all bytes on reads regardless of the

byte enables, and Core-logic may merge host processor

writes into this range without causing errors.

2:1 R-IW-Dx Type AGP3.0 allows the target to support either a 64-bit or a 32-bit