Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
17
Table 5: Signal List
AGP2.0 Signal AGP3.0 Signal Signaling Scheme in
AGP3.0
Max Signaling
Rate in AGP3.0
Assertion Level in
AGP3.0
SBA SBA#1 AGP3.0 signaling 533MT/s/Source Synch 1=Low; 0=High
SB_STB, SB_STB# SB_STBF, SB_STBS AGP3.0 Signaling 266MHz 1=High; 0=Low
AD AD AGP3.0 Signaling 533MT/s/Source Synch 1=High; 0=Low
AD_STB[1:0],
AD_STB#[1:0]
AD_STBF[1:0],
AD_STBS[1:0]
DBI_HI, DBI_LO
AGP3.0 Signaling 266 MHz 1=High, 0=Low
C/BE# C#/BE AGP3.0 Signaling 533MT/s/Source Synch C#: 1=Low; 0=High
BE: 1=High; 0=Low
ST, PAR ST, PAR AGP3.0 Signaling 66MHz/Common Clock 1=High;0=Low
FRAME#, TRDY#, IRDY#,
STOP#, GNT#,
DEVSEL#, PERR#,
SERR#, REQ#, IDSEL,
RBF#, WBF#
FRAME, TRDY, IRDY,
STOP, GNT, DEVSEL,
PERR, SERR, REQ,
IDSEL, RBF, WBF
AGP3.0 Signaling 66MHz/Common Clock 1=High;0=Low
CLK CLK Same as AGP2.0 66 MHz Same as AGP
RST#, INTA#, INTB#,
PME#, TYPEDET#
Same as AGP Same as AGP2.0- Asynch/Static Same as AGP
2.1.1 New and Redefined Signals
AGP3.0 adds and redefines the following new signals to support the change in the signaling scheme. The new
signals replace reserved pins on the current AGP connector.
1
It is important to note that SBA encodings for address and requests are inverted on AGP3.0 relative to AGP. This is
because a NOP or idle state on this interface is all 1s, so in AGP3.0 this equates to a 0V level.