Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
23
transactions, designs are strongly encouraged to not delay the assertion of IRDY or TRDY by
more than 8 clock cycles, i.e. beyond T10.
6. Once the Core-logic asserts IRDY it must keep it asserted until it samples TRDY asserted. It will
then de-assert IRDY to end the calibration cycle.
7. Similarly, once the Graphics chip asserts TRDY, it must continue to assert it until it samples IRDY
asserted upon which it will de-assert TRDY and end the calibration cycle.
8. A new transaction may begin in the clock cycle immediately following the de-assertion of IRDY
and TRDY on the AGP interface.
The timing diagram below illustrates this sequence.