Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
26
Figure 2-6: SBA Calibration When SBA Strobes are Stopped
2.1.4.2 Initial Calibration of Buffers
When the system comes out of a power-up reset, the AGP3.0 I/O buffers need to be calibrated prior to
any operation (PCI or AGP) on the interface. A minimum of 100 microseconds should be allowed
following removal of AGP Reset condition during which the interface is locked in the unasserted state.
During this time interval, no AGP or PCI cycles are allowed. The Master (graphics chip) and Target
(core-logic) use the time after reset to do the initial calibration of their buffers based on the selected
mode of operation (AGP2.0V or AGP3.0). See section 2.4.2 for details on mode selection.
The core-logic cannot initiate any cycle before 100 microseconds after reset. There is no maximum
delay. The Master cannot initiate any AD cycles or SBA cycles (or PIPE# in AGP2.0 mode) until AGP
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T19 T20 T21 T22
AGP CLK
ST[2:0]
GNT
IRDY
TRDY
SBA[7:0]#
110
000
AD Calibration Cycle
No SBA Sync Allowed during this period
Target tests for SBA
activity
5 clocks 4 clocks
12 clocks
4 clocks minimum
(5 in this example)
Master & Target may
calibrate
SBA (SB_STBx may glitch)
SBA Sync Allowed