Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
31
Legend:
R = Required
O = Optional
I = Internal signal
NS = Not supported
A shaded cell indicates that the signal is not applicable to the function.
/ NOTE
1. The AGP Master does not require RBF if it can always accept the return of Read data.
2. The AGP Master does not require WBF if it always can accept the first block of FW data.
3. ST signals are only optional to the PCI master if no AGP support is implemented.
2.2.1 IDSEL Usage for Configuration
Initialization of an AGP device occurs via the configuration mechanism defined by the PCI Local Bus
Specification. An AGP Master is composed of a PCI Target interface and an AGP Master interface.
(Optionally, the AGP Master can also include a PCI Master interface). The PCI target interface follows
the PCI Local Bus Specification. This requires the device to respond to a PCI configuration transaction
when a configuration request (read or write) is decoded and AD01 and AD00 are both “0” and the
device’s IDSEL is asserted.
Since IDSEL is not a signal on the AGP connector, it must be connected to AD16 on the graphics
component. The designer of the AGP Master must be careful as to how this connection is made since
the AD lines are running at very high speeds. This connection between IDSEL and AD16 must not
electrically load AD16 in the physical interconnect between the core-logic and the graphics chip.
2.3 Transaction and Protocol Changes
Most changes in transactions and protocol result from the 8X data rate and removal of certain
transaction types. These changes are described in this section. Additional enhancements in
transaction types specific to workstation platforms are described in Appendix A: Workstation
Enhancements.
AGP references two types of transactions: AGP transactions and PCI transactions. AGP
transactions use AGP protocol semantics and include transfers initiated by the AGP Master using the
SBA Interface as well as core-logic initiated Fast-Writes. PCI transactions refer to transactions initiated
by the AGP Master or core-logic that use the PCI Protocol semantics.
2.3.1 AGP Transaction Requests
In the past, AGP transactions could be generated using two modes: PIPE and SBA. The core-logic had
to support both modes, while the AGP Master could optionally use either. AGP3.0 does not support
using PIPE mode to generate an AGP request. This leaves only the SBA scheme, which is no longer
optional. When operating in AGP3.0 mode, the PIPE# signal pin on the AGP connector is given a new
function, DBI-HI. A “universal” implementation must multiplex PIPE# and DBI_HI onto the same signal pin
and select the right function based on the signaling mode of operation.