Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
33
The “CCCC” field contains the Bus operation or request as itemized in Table 12.
Table 12: AGP3.0/AGP2.0 Bus Requests
CCCC AGP2.0 AGP3.0
0000 Read (low -priority) Read (Asynchronous
5
)
0001 Read (high-priority) Reserved
0010 Reserved Reserved
0011 Reserved Reserved
3
0100 Write (low -priority) Write (Asynchronous
5
)
0101 Write (high-priority) Reserved
0110 Reserved Reserved
3
0111 Reserved Reserved
3
1000 Long Read (low -priority) Reserved
1001 Long Read (high-priority) Reserved
1010 Flush (low -priority) Flush
1011 Reserved Reserved
1100 Fence (low -priority) Fence (for reads & writes)
1101
4
Reserved ) Reserved
1110 Reserved Reserved
3
1111 Reserved Reserved
Associated with the previous requests are the status codes from the core-logic to signal the completion
response for the disconnected transaction. Certain codes are reserved in AGP3.0. The codes listed as
ST[2:0] on the signal interface are common clock signals that are valid only when GNT is asserted.
These codes are shown in Table 13.
Table 13: Status Codes
Status Code ST[2:0] AGP2.0 Usage AGP3.0 Usage
000 Low Priority Read Read (Asynchronous
5
)
001 High Priority Read Reserved
010 Low Priority Write Write (Asynchronous
5
)
011 High Priority Write Reserved
100 Reserved Reserved
6
101 Reserved Reserved
6
110 Reserved Calibration Cycle
111 AGP Master can start PCI Transaction using FRAME#
or PIPE#.
AGP3.0 Master can start PCI Transaction using
FRAME.
As in AGP2.0, the AGP3.0 read access granularity is 8-bytes. The AGP3.0 address must be naturally
aligned to 8-byte boundaries. Again, similar to AGP2.0, the read transfer time on AGP3.0 is in multiples
of the common clock. The core-logic ensures that for read transfers that take less than a common clock
cycle, the unused portion of the cycle is padded with meaningless data. The strobes continue to run for
the entire cycle, and the byte enables (C#/BE) are driven only during the meaningful data portion. The
critical data (the first data associated with the requested address) will always be driven first followed by
3
See Table 38 in Appendix A for optional use of these reserved codes.
4
This encoding is used on the C#/BE[3:0] for performing a “Dual Address Cycle” on a FRAME based PCI transaction. It is
reserved for AGP requests.
5
The term “asynchronous” differentiates this transaction type from the isochronous transactions described in Appendix A
where latency and throughput are deterministic.
6
See 4.1.6in Appendix A for optional use of these reserved codes.