Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
36
CLK
1 2 3 4 5 6 7 8 9
RBF
TRDY
GNT
000 000
xxx
xxx
000 000000 000 00
xx
ST[2::0]
8-29
AD
AD_STBF
RD1 32B | RD2 64B
|
STALL
|
RD3 32B
|
RD4 32B
|
RD5 32B
|
RD6
AD_STBS
Figure 2-9: Use of RBF in Read Transaction Control
In Figure 2-9, RBF is not able to stop the two pipelined GNTs from completing their transactions. (These
are labeled RD1 and RD2 in the diagram.)
RD1 performed a 32-byte transfer followed by an RD2 that performed a 64-byte transfer (too small to
initiate IRDY flow control). RBF managed to block the third data transfer (labeled RD3) from starting by
inserting two wait states.
2.3.3.4 Buffer-Full Flow Control on Core-logic Fast Writes
The target of the Fast Writes (AGP device) also has a signal called WBF that is used, if required, to
prevent the start of a Fast write transaction. The arbiter in the core-logic checks the status of WBF
before initiating a Fast Write transaction. If WBF is asserted at this time, the start of the write is
suppressed.
The only change from AGP is that the target of the Fast Writes (AGP Device) must have twice the
minimum buffering specified for AGP2.0 data rates before a fast write stall takes effect. This amounts
to 160 bytes for AGP3.0 versus 80 bytes for AGP2.0.
2.3.4 Ordering Rule Changes
Ordering rules specify the relationship between concurrently active transactions as they progress to
completion through the platform. AGP3.0 follows the same ordering rules as AGP2.0 except for AGP
writes (formerly known in AGP as low priority writes).
An AGP write is considered to have completed if it has reached a point of global visibility where any
future read access to the system memory location targeted by this write gets the modified data. Note
that the definition for completion does not require that the actual physical memory location be updated
only that the new data is globally visible.
AGP requires that the completion of low priority writes occur in the same order as the issued requests
from the Master. The AGP3.0 specification, however, does not require that the core-logic complete the