Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
38
2.4 Platform Architecture Differences
This section deals with changes to AGP that have platform level dependencies. These include support
for hardware- enforced coherency, peer-to-peer access models, and system configuration issues.
2.4.1 Hardware Enforced Cache Coherency
The AGP Master performs AGP or PCI transactions that are directed at system memory, with a single
address space being associated with all these transactions. In this address space, a contiguous region
may be specified where an AGP address is re-mapped to a different physical memory address using a
platform defined structure called the Graphics Address Re-map Table (or GART). The re-mapping
region is called the AGP aperture.
The system memory has cacheable regions that can be kept coherent through hardware and software
means. Hardware enforced cache coherency, such as snooping, is the responsibility of the core-logic
and all caching agents. The performance of hardware-enforced coherency schemes varies between
platforms. The appropriate use of the hardware-enforced coherency feature is the responsibility of the
graphics card’s device driver.
Hardware-enforced coherency for AGP Master accesses to system memory address space is as
follows:
1. The core-logic must implement hardware-enforced coherency on all AGP Master transactions
(AGP and PCI types) targeted outside the AGP aperture region.
2. For any AGP3.0 Master accesses inside the AGP3.0 aperture region, hardware-enforced
coherency is optional. Appendix B: Workstation Programming Model describes the scheme
used to implement this optional feature on workstation platforms.