Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
48
Bits Access Field Description
AGP3.0_MODE = 0, the RATE field (AGPSTAT[2:0]) and
DRATE field (AGPCMD[2:0]) in both the master and target
must function as defined by the AGP Interface Specification
V2.0 for compatibility with existing software.
2:0 R-IW RATE Data Rate Support (RATE) -
AGPSTAT[3] Code Speed Supported
0 xxx See AGP2.0 Specs
1 001 4x
1 010 8x
1 011 4, and 8x
1 All other
codes
Reserved
2.7.5 AGP_CMD: AGP COMMAND REGISTER
Offset: CAPPTR + 08h
Size: 4 bytes
Table 28: Command Register
Bits Access Field Description
31:24 MST: R-W-D’0
TGT: RZ-IW
PRQ Master: The PRQ field must be programmed with the
maximum number of AGP3.0 command requests the
master is allowed to enqueue in the target. “0” means a
depth of one entry, while FFh means a depth of 256
entries.
Target: IGNORED.
23:17 RZ-MW Reserved Always returns 0 when read; write operations have no
effect.
16 RZ-MW Reserved Always returns 0 when read; write operations have no
effect.
15:13 MST: R-W-D’0
TGT: RZ-IW-D’x
PARQSZ MASTER ONLY: Programmed based on ARQSZ in
TARGET’s AGPSTAT[15:13]. LOG2 of the optimum
asynchronous request size in bytes minus 4 to be used
with the target. The MASTER should attempt to issue a
group of sequential back-to-back asynchronous requests
that total to this size and for which the group is naturally
aligned.
Optimum_request_size = 2 ^ (ARQSZ+4)
If ARQSZ is zero, then the target has no recommendation.
12:10 MST: RZ-IW
TGT: R-W-
D’000
PCAL_Cycle TARGET ONLY: Programmed with period for core-logic
initiated bus cycle for calibrating I/O buffers for both
master and target. This value is updated with the smaller
of the value in CAL_CYCLE from Master’s/Target’s
AGPSTAT. The translations of the encoding are the same
as in CAL_CYCLE.
PCAL_CYCLE is set to 111 (Calibration Cycle Disabled)
by s/w only if both Target and Master have
AGPSTAT.CAL_CYCLE = 111.