Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
52
Both GC_DET#, and MB_DET# are of the asynchronous signal type. The GC_DET# signal is a static
signal supplied from the graphics card to indicate to the motherboard and/or core-logic that the AGP3.0
signaling and protocol are supported. Likewise, the MB_DET# signal is a static signal supplied from the
motherboard or core-logic to indicate to the graphics card and/or AGP3.0 Master that the AGP3.0
signaling and protocol are supported.
The DBI_HI and DBI_LO signals are source synchronous signals.
Source Synchronous Capable Signals
AD[31::16]
C#/BE[1::0]
AD_STBF[0]/AD_STBS[0]
AD[15::0]
C#/BE[3::2]
AD_STBF[1]/AD_STBS[1]
SBA[7::0]#
SB_STBF/SB_STBS
Common Clock Signals
PAR
ST[2::0]
RBF
WBF
TRDY
IRDY
GNT
FRAME
DEVSEL
PERR
SERR
REQ
STOP
Asynchronous
AGP8X
Master
(Graphics
Controller)
AGP8X
Target
(Core-
logic)
RST RST
RST
INTA#
INTB#
PME#
INTA#
INTB#
PME#
OVRCNT#
USB+
OVERCNT#
USB+
USB-
USB-
CLK
66MHz CLK
Vrefgc
Vrefcg
TYPEDET#
DBI_LO
DBI_HI
MB_DET#
GC_DET#
Figure 3-1: AGP3.0 Logical Diagram
Table 30 lists the various signals of the AGP3.0 interface and identifies the clock domain to which each
signal belongs. Signals identified with a double asterisk (**) specification have inverted their signaling