Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
8
List of Figures
Figure 2-1: 8X SBA Addressing Showing Three Consecutive SBA Requests........................................19
Figure 2-2: 8X Data Transfers on AD Interface.......................................................................................19
Figure 2-3: Minimum TRDY and AD_STB Timing Relationship..............................................................21
Figure 2-4: AGP3.0 Calibration Cycle......................................................................................................24
Figure 2-5: SB_STB Stopping and Starting Sequence............................................................................25
Figure 2-6: SBA Calibration When SBA Strobes are Stopped................................................................26
Figure 2-7: Usage of DBI on Source Synchronous Transfers.................................................................28
Figure 2-8: Fast-Write Showing Wait State Insertion..............................................................................35
Figure 2-9: Use of RBF in Read Transaction Control..............................................................................36
Figure 2-10: AGP3.0 Configuration Register Space................................................................................43
Figure 3-1: AGP3.0 Logical Diagram .......................................................................................................52
Figure 3-2: Common Clock Transfer Timings.........................................................................................55
Figure 3-3: Source Synchronous Mode Time Domain............................................................................56
Figure 3-4: Transmit Strobe/Data Timing for 8X Source Synchronous Timing ......................................57
Figure 3-5: Receive Strobe/Data Timings for 8X Source Synchronous Timing......................................58
Figure 3-6: Minimum and Maximum Inner to Outer Loop Receive Timings ............................................58
Figure 3-7: Composite Receive Timing for 8X.........................................................................................60
Figure 3-8: AGP3.0 Voltage Swing...........................................................................................................63
Figure 3-9: Determination of Device RON Values...................................................................................64
Figure 3-10: Driving the Interface High.....................................................................................................65
Figure 3-11: A Quiescent Interface or Being Driven Low ........................................................................65
Figure 3-12: Spacing to Height Definitions for Stripline and Microstrip Implementations........................68
Figure 3-13: Clock Skew Diagram...........................................................................................................69
Figure 3-14: AGP3.0 Standard Buffer Test Load.....................................................................................78
Figure 3-15: . Input Timing Measurement................................................................................................78
Figure 3-16: General Signal Integrity Waveform.....................................................................................83
Figure 3-17: Signal Integrity Requirements..............................................................................................84
Figure 3-18: Strobe Ringback Examples................................................................................................84
Figure 3-19: Address/Data Ringback Examples ....................................................................................85
Figure 3-20: Open-circuit Voltage............................................................................................................87
Figure 3-21: V/I Curve for AGP3.0 Receiver Termination Device............................................................89
Figure 3-22: V/I Curve for AGP3.0 Transmitter Pull-up............................................................................90
Figure 4-1: Isochronous Latency Determines Transfer Occurances .....................................................99
Figure 4-2: N, Y, and L Values Determine Platform Isochronous Class-level Service...........................99
Figure 4-3: AGP3.0 Fanout Bridge Connections ...................................................................................105
Figure 4-4: Potential Fan-Out Bridge Delays of Isochronous Periods for AGP3.0 Devices .................107
Figure 4-5: Fan-out Bridge Scheme Example.......................................................................................112
Figure 5-1: AGP3.0 Generalized Logical System Overview..................................................................113
Figure 5-2: AGP Graphics Aperture Model.............................................................................................116
Figure 5-3: Location of AGP3.0 Capabilities ..........................................................................................123
Figure 5-4: AGP3.0 Configuration Register Space................................................................................124